Lines Matching full:sx
272 // SX-Aurora has following fields.
548 def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),
549 !strconcat(opcStr, " $sx, $sy, $sz"),
550 [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>;
554 def ri : RR<opc, (outs RCo:$sx), (ins RCi:$sz, immOp:$sy),
555 !strconcat(opcStr, " $sx, $sy, $sz"),
556 [(set Tyo:$sx, (OpNode Tyi:$sz, (Tyi immOp:$sy)))]>;
558 def rm : RR<opc, (outs RCo:$sx), (ins RCi:$sy, mOp:$sz),
559 !strconcat(opcStr, " $sx, $sy, $sz"),
560 [(set Tyo:$sx, (OpNode Tyi:$sy, (Tyi mOp:$sz)))]>;
562 def im : RR<opc, (outs RCo:$sx), (ins immOp:$sy, mOp:$sz),
563 !strconcat(opcStr, " $sx, $sy, $sz"),
564 [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), (Tyi mOp:$sz)))]> {
579 def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),
580 !strconcat(opcStr, " $sx, $sy, $sz"),
581 [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>;
583 def ir : RR<opc, (outs RCo:$sx), (ins immOp:$sy, RCi:$sz),
584 !strconcat(opcStr, " $sx, $sy, $sz"),
585 [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), Tyi:$sz))]>;
587 def rm : RR<opc, (outs RCo:$sx), (ins RCi:$sy, mOp:$sz),
588 !strconcat(opcStr, " $sx, $sy, $sz"),
589 [(set Tyo:$sx, (OpNode Tyi:$sy, (Tyi mOp:$sz)))]>;
591 def im : RR<opc, (outs RCo:$sx), (ins immOp:$sy, mOp:$sz),
592 !strconcat(opcStr, " $sx, $sy, $sz"),
593 [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), (Tyi mOp:$sz)))]>;
626 def rr : RR<opc, (outs RC:$sx), (ins RC:$sz, I32:$sy),
627 !strconcat(opcStr, " $sx, $sz, $sy"),
628 [(set Ty:$sx, (OpNode Ty:$sz, i32:$sy))]>;
630 def mr : RR<opc, (outs RC:$sx), (ins mimm:$sz, I32:$sy),
631 !strconcat(opcStr, " $sx, $sz, $sy"),
632 [(set Ty:$sx, (OpNode (Ty mimm:$sz), i32:$sy))]>;
634 def ri : RR<opc, (outs RC:$sx), (ins RC:$sz, uimm7:$sy),
635 !strconcat(opcStr, " $sx, $sz, $sy"),
636 [(set Ty:$sx, (OpNode Ty:$sz, (i32 uimm7:$sy)))]>;
638 def mi : RR<opc, (outs RC:$sx), (ins mimm:$sz, uimm7:$sy),
639 !strconcat(opcStr, " $sx, $sz, $sy"),
640 [(set Ty:$sx, (OpNode (Ty mimm:$sz), (i32 uimm7:$sy)))]>;
645 let Constraints = "$hi = $sx", DisableEncoding = "$hi", hasSideEffects = 0 in
647 def rrr : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, I32:$sy),
648 !strconcat(opcStr, " $sx, $sz, $sy")>;
650 def rmr : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, I32:$sy),
651 !strconcat(opcStr, " $sx, $sz, $sy")>;
653 def rri : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, uimm7:$sy),
654 !strconcat(opcStr, " $sx, $sz, $sy")>;
656 def rmi : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, uimm7:$sy),
657 !strconcat(opcStr, " $sx, $sz, $sy")>;
662 let Constraints = "$low = $sx", DisableEncoding = "$low", hasSideEffects = 0 in
664 def rrr : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, I32:$sy),
665 !strconcat(opcStr, " $sx, $sz, $sy")>;
667 def mrr : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, I32:$sy),
668 !strconcat(opcStr, " $sx, $sz, $sy")>;
670 def rri : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, uimm7:$sy),
671 !strconcat(opcStr, " $sx, $sz, $sy")>;
673 def mri : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, uimm7:$sy),
674 !strconcat(opcStr, " $sx, $sz, $sy")>;
682 def r : RR<opc, (outs RC:$sx), (ins RC:$sz), !strconcat(opcStr, " $sx, $sz"),
683 [(set Ty:$sx, (OpNode Ty:$sz))]>;
685 def m : RR<opc, (outs RC:$sx), (ins mimm:$sz),
686 !strconcat(opcStr, " $sx, $sz"),
687 [(set Ty:$sx, (OpNode (Ty mimm:$sz)))]>;
692 let Constraints = "$sx = $sd", DisableEncoding = "$sd", hasSideEffects = 0 in
694 def rr : RR<opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, RC:$sd),
695 !strconcat(opcStr, " $sx, $sy, $sz")>;
697 def ir : RR<opc, (outs RC:$sx), (ins simm7:$sy, RC:$sz, RC:$sd),
698 !strconcat(opcStr, " $sx, $sy, $sz")>;
700 def rm : RR<opc, (outs RC:$sx), (ins RC:$sy, mimm:$sz, RC:$sd),
701 !strconcat(opcStr, " $sx, $sy, $sz")>;
703 def im : RR<opc, (outs RC:$sx), (ins simm7:$sy, mimm:$sz, RC:$sd),
704 !strconcat(opcStr, " $sx, $sy, $sz")>;
714 def ri : RR<opc, (outs RC:$sx), (ins RC:$sz, uimm1:$sy),
715 !strconcat(opcStr, " $sx, $sz, $sy"),
716 [(set Ty:$sx, (OpNode Ty:$sz, (i32 uimm1:$sy)))]>;
718 def mi : RR<opc, (outs RC:$sx), (ins mimm:$sz, uimm1:$sy),
719 !strconcat(opcStr, " $sx, $sz, $sy"),
720 [(set Ty:$sx, (OpNode (Ty mimm:$sz), (i32 uimm1:$sy)))]>;
725 let Constraints = "$sx = $sd", DisableEncoding = "$sd", hasSideEffects = 0,
730 def rr : RR<opc, (outs I64:$sx), (ins CCOp:$cfw, RC:$sy, I64:$sz, I64:$sd),
731 !strconcat(opcStr, " $sx, $sz, $sy"),
732 [(set i64:$sx, (OpNode Ty:$sy, i64:$sz, i64:$sd,
735 def ir : RR<opc, (outs I64:$sx),
737 !strconcat(opcStr, " $sx, $sz, $sy"),
738 [(set i64:$sx, (OpNode (Ty immOp:$sy), i64:$sz, i64:$sd,
741 def rm : RR<opc, (outs I64:$sx),
743 !strconcat(opcStr, " $sx, $sz, $sy"),
744 [(set i64:$sx, (OpNode Ty:$sy, (i64 mimm:$sz), i64:$sd,
747 def im : RR<opc, (outs I64:$sx),
749 !strconcat(opcStr, " $sx, $sz, $sy"),
750 [(set i64:$sx, (OpNode (Ty immOp:$sy), (i64 mimm:$sz), i64:$sd,
760 def r : RR<opc, (outs RCo:$sx), (ins RDOp:$rd, RCi:$sy),
761 !strconcat(opcStr, "${rd} $sx, $sy")> {
767 def i : RR<opc, (outs RCo:$sx), (ins RDOp:$rd, simm7:$sy),
768 !strconcat(opcStr, "${rd} $sx, $sy")> {
781 def r : RR<opc, (outs RCo:$sx), (ins RCi:$sy),
782 !strconcat(opcStr, " $sx, $sy"),
783 [(set Tyo:$sx, (OpNode Tyi:$sy))]>;
785 def i : RR<opc, (outs RCo:$sx), (ins simm7:$sy),
786 !strconcat(opcStr, " $sx, $sy")>;
791 let sx = 0, hasSideEffects = 0 in
808 let Constraints = "$sx = $sd", DisableEncoding = "$sd",
813 def r : RRM<opc, (outs RC:$sx), (ins (MEM $sz, $imm32):$addr, RC:$sy, RC:$sd),
814 !strconcat(opcStr, " $sx, $addr, $sy"),
815 [(set Ty:$sx, (OpNode ADDR:$addr, Ty:$sy, Ty:$sd))]>;
817 def i : RRM<opc, (outs RC:$sx), (ins (MEM $sz, $imm32):$addr, immOp:$sy, RC:$sd),
818 !strconcat(opcStr, " $sx, $addr, $sy"),
819 [(set Ty:$sx, (OpNode ADDR:$addr, (Ty immOp:$sy), Ty:$sd))]>;
897 def rr : RR<opc, (outs RC:$sx), (ins RC:$sy, RC:$sz),
898 !strconcat(opcStr, " $sx, $sy, $sz")>;
899 let cy = 0 in def ir : RR<opc, (outs RC:$sx), (ins simm7:$sy, RC:$sz),
900 !strconcat(opcStr, " $sx, $sy, $sz")>;
901 let cz = 0 in def rz : RR<opc, (outs RC:$sx), (ins RC:$sy, zero:$sz),
902 !strconcat(opcStr, " $sx, $sy, $sz")>;
904 def iz : RR<opc, (outs RC:$sx), (ins simm7:$sy, zero:$sz),
905 !strconcat(opcStr, " $sx, $sy, $sz")>;
912 def rrr : RR<opc, (outs), (ins RC:$sy, RC:$sz, RC:$sx),
913 !strconcat(opcStr, " $sx, $sy, $sz")>;
914 let cy = 0 in def irr : RR<opc, (outs), (ins simm7:$sy, RC:$sz, RC:$sx),
915 !strconcat(opcStr, " $sx, $sy, $sz")>;
916 let cz = 0 in def rzr : RR<opc, (outs), (ins RC:$sy, zero:$sz, RC:$sx),
917 !strconcat(opcStr, " $sx, $sy, $sz")>;
919 def izr : RR<opc, (outs), (ins simm7:$sy, zero:$sz, RC:$sx),
920 !strconcat(opcStr, " $sx, $sy, $sz")>;
923 let hasSideEffects = 1, Constraints = "$sx = $sx_in", DisableEncoding = "$sx_in" in
925 def rrr : RR<opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, RC:$sx_in),
926 !strconcat(opcStr, " $sx, $sy, $sz")>;
927 let cy = 0 in def irr : RR<opc, (outs RC:$sx), (ins simm7:$sy, RC:$sz, RC:$sx_in),
928 !strconcat(opcStr, " $sx, $sy, $sz")>;
929 let cz = 0 in def rzr : RR<opc, (outs RC:$sx), (ins RC:$sy, zero:$sz, RC:$sx_in),
930 !strconcat(opcStr, " $sx, $sy, $sz")>;
932 def izr : RR<opc, (outs RC:$sx), (ins simm7:$sy, zero:$sz, RC:$sx_in),
933 !strconcat(opcStr, " $sx, $sy, $sz")>;
941 def ri : RR<opc, (outs RC:$sx), (ins RC:$sy, uimm3:$sz),
942 !strconcat(opcStr, " $sx, $sy, $sz")>;
943 let cy = 0 in def ii : RR<opc, (outs RC:$sx), (ins simm7:$sy, uimm3:$sz),
944 !strconcat(opcStr, " $sx, $sy, $sz")>;
950 def ri : RRMHM<opc, (outs RC:$sx), (ins (MEMriHM $sz, $imm32):$addr),
951 !strconcat(opcStr, " $sx, $addr")>;
953 def zi : RRMHM<opc, (outs RC:$sx), (ins (MEMziHM $sz, $imm32):$addr),
954 !strconcat(opcStr, " $sx, $addr")>;
960 def ri : RRMHM<opc, (outs), (ins (MEMriHM $sz, $imm32):$addr, RC:$sx),
961 !strconcat(opcStr, " $sx, $addr")>;
963 def zi : RRMHM<opc, (outs), (ins (MEMziHM $sz, $imm32):$addr, RC:$sx),
964 !strconcat(opcStr, " $sx, $addr")>;
970 // Define all scalar instructions defined in SX-Aurora TSUBASA Architecture
981 def rri : RM<opc, (outs RC:$sx), (ins (MEMrri $sz, $sy, $imm32):$addr),
982 !strconcat(opcStr, " $sx, $addr"), []>;
984 def rii : RM<opc, (outs RC:$sx), (ins (MEMrii $sz, $sy, $imm32):$addr),
985 !strconcat(opcStr, " $sx, $addr"), []>;
987 def zri : RM<opc, (outs RC:$sx), (ins (MEMzri $sz, $sy, $imm32):$addr),
988 !strconcat(opcStr, " $sx, $addr"), []>;
990 def zii : RM<opc, (outs RC:$sx), (ins (MEMzii $sz, $sy, $imm32):$addr),
991 !strconcat(opcStr, " $sx, $addr"), []> {
1017 def rri : RM<opc, (outs RC:$sx), (ins (MEMrri $sz, $sy, $imm32):$addr),
1018 !strconcat(opcStr, " $sx, $addr"),
1019 [(set Ty:$sx, (OpNode ADDRrri:$addr))]>;
1021 def rii : RM<opc, (outs RC:$sx), (ins (MEMrii $sz, $sy, $imm32):$addr),
1022 !strconcat(opcStr, " $sx, $addr"),
1023 [(set Ty:$sx, (OpNode ADDRrii:$addr))]>;
1025 def zri : RM<opc, (outs RC:$sx), (ins (MEMzri $sz, $sy, $imm32):$addr),
1026 !strconcat(opcStr, " $sx, $addr"),
1027 [(set Ty:$sx, (OpNode ADDRzri:$addr))]>;
1029 def zii : RM<opc, (outs RC:$sx), (ins (MEMzii $sz, $sy, $imm32):$addr),
1030 !strconcat(opcStr, " $sx, $addr"),
1031 [(set Ty:$sx, (OpNode ADDRzii:$addr))]>;
1048 defm LDLSX : LOADm<"ldl.sx", 0x03, I32, i32, load>;
1054 defm LD2BSX : LOADm<"ld2b.sx", 0x04, I32, i32, sextloadi16>;
1060 defm LD1BSX : LOADm<"ld1b.sx", 0x05, I32, i32, sextloadi8>;
1075 def rri : RM<opc, (outs), (ins (MEMrri $sz, $sy, $imm32):$addr, RC:$sx),
1076 !strconcat(opcStr, " $sx, $addr"),
1077 [(OpNode Ty:$sx, ADDRrri:$addr)]>;
1079 def rii : RM<opc, (outs), (ins (MEMrii $sz, $sy, $imm32):$addr, RC:$sx),
1080 !strconcat(opcStr, " $sx, $addr"),
1081 [(OpNode Ty:$sx, ADDRrii:$addr)]>;
1083 def zri : RM<opc, (outs), (ins (MEMzri $sz, $sy, $imm32):$addr, RC:$sx),
1084 !strconcat(opcStr, " $sx, $addr"),
1085 [(OpNode Ty:$sx, ADDRzri:$addr)]>;
1087 def zii : RM<opc, (outs), (ins (MEMzii $sz, $sy, $imm32):$addr, RC:$sx),
1088 !strconcat(opcStr, " $sx, $addr"),
1089 [(OpNode Ty:$sx, ADDRzii:$addr)]>;
1118 def STQrii : Pseudo<(outs), (ins MEMrii:$addr, F128:$sx),
1119 "# pseudo stq $sx, $addr",
1120 [(store f128:$sx, ADDRrii:$addr)]>;
1133 defm DLDLSX : LOADm<"dldl.sx", 0x0b, I32, i32, load>;
1186 let sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1 in
1198 defm ADDSWSX : RRm<"adds.w.sx", 0x4A, I32, i32, add>;
1209 defm SUBSWSX : RRNCm<"subs.w.sx", 0x5A, I32, i32, sub>;
1220 defm MULSWSX : RRm<"muls.w.sx", 0x4B, I32, i32, mul>;
1234 defm DIVSWSX : RRNCm<"divs.w.sx", 0x7B, I32, i32, sdiv>;
1245 defm CMPSWSX : RRNCm<"cmps.w.sx", 0x7A, I32, i32>;
1252 // cx: sx/zx, cw: max/min
1253 defm MAXSWSX : RRm<"maxs.w.sx", 0x78, I32, i32, smax>;
1255 let cw = 1 in defm MINSWSX : RRm<"mins.w.sx", 0x78, I32, i32, smin>;
1344 defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>;
1351 defm SRAWSX : RRIm<"sra.w.sx", 0x76, I32, i32, sra>;
1418 // cx: double/float, cw: sx/zx, sz{0-3} = round
1420 defm CVTWDSX : CVTRDm<"cvt.w.d.sx", 0x4E, I32, I64>;
1424 defm CVTWSSX : CVTRDm<"cvt.w.s.sx", 0x4E, I32, F32>;
1494 let Defs = [SX10], sx = 10 /* SX10 */, cy = 0, sy = 0, imm32 = 0,
1505 def SIC : RR<0x28, (outs I32:$sx), (ins), "sic $sx">;
1508 let sx = 0, cz = 0, sz = 0, hasSideEffects = 1, Defs = [PSW] in
1513 def SPM : RR<0x2a, (outs I64:$sx), (ins), "spm $sx">;
1516 let sx = 0, cz = 0, sz = 0, hasSideEffects = 1, Defs = [PSW] in {
1523 def SFR : RR<0x29, (outs I64:$sx), (ins), "sfr $sx">;
1527 def SMIR : RR<0x22, (outs I64:$sx), (ins MISC:$sy), "smir $sx, $sy">;
1531 let sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 in
1535 let sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1 in {
2170 def any_broadcast : PatFrag<(ops node:$sx),
2171 (vec_broadcast node:$sx, (i32 srcvalue))>;