Lines Matching full:ve
1 //===-- VEISelLowering.cpp - VE DAG Lowering Implementation ---------------===//
9 // This file implements the interfaces that VE uses to lower LLVM code into a
39 #define DEBUG_TYPE "ve-lower"
85 addRegisterClass(MVT::i32, &VE::I32RegClass); in initRegisterClasses()
86 addRegisterClass(MVT::i64, &VE::I64RegClass); in initRegisterClasses()
87 addRegisterClass(MVT::f32, &VE::F32RegClass); in initRegisterClasses()
88 addRegisterClass(MVT::f64, &VE::I64RegClass); in initRegisterClasses()
89 addRegisterClass(MVT::f128, &VE::F128RegClass); in initRegisterClasses()
93 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses()
94 addRegisterClass(MVT::v256i1, &VE::VMRegClass); in initRegisterClasses()
95 addRegisterClass(MVT::v512i1, &VE::VM512RegClass); in initRegisterClasses()
103 // VE doesn't have i1 sign extending load. in initSPUActions()
111 // VE doesn't have floating point extload/truncstore, so expand them. in initSPUActions()
119 // VE doesn't have fp128 load/store, so expand them in custom lower. in initSPUActions()
153 // VE doesn't have BRCOND in initSPUActions()
163 // VE has no REM or DIVREM operations. in initSPUActions()
169 // VE has no SHL_PARTS/SRA_PARTS/SRL_PARTS operations. in initSPUActions()
174 // VE has no MULHU/S or U/SMUL_LOHI operations. in initSPUActions()
181 // VE has no CTTZ, ROTL, ROTR operations. in initSPUActions()
186 // VE has 64 bits instruction which works as i64 BSWAP operation. This in initSPUActions()
191 // VE has only 64 bits instructions which work as i64 BITREVERSE/CTLZ/CTPOP in initSPUActions()
199 // VE has only 64 bits instructions which work as i64 AND/OR/XOR operations. in initSPUActions()
212 // VE doesn't have instructions for fp<->uint, so expand them by llvm in initSPUActions()
229 // VE doesn't have following floating point operations. in initSPUActions()
235 // VE doesn't have fdiv of f128. in initSPUActions()
246 // VE doesn't have following floating point math functions. in initSPUActions()
257 // VE has single and double FMINNUM and FMAXNUM in initSPUActions()
284 // VE doesn't have follwing instructions. in initSPUActions()
415 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerReturn()
492 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerFormalArguments()
559 .Case("sp", VE::SX11) // Stack pointer in getRegisterByName()
560 .Case("fp", VE::SX9) // Frame pointer in getRegisterByName()
561 .Case("sl", VE::SX8) // Stack limit in getRegisterByName()
562 .Case("lr", VE::SX10) // Link register in getRegisterByName()
563 .Case("tp", VE::SX14) // Thread pointer in getRegisterByName()
564 .Case("outer", VE::SX12) // Outer regiser in getRegisterByName()
565 .Case("info", VE::SX17) // Info area register in getRegisterByName()
566 .Case("got", VE::SX15) // Global offset table register in getRegisterByName()
567 .Case("plt", VE::SX16) // Procedure linkage table register in getRegisterByName()
587 // VE target does not yet support tail call optimization. in LowerCall()
605 // VE requires to use both register and stack for varargs or no-prototyped in LowerCall()
637 // VE needs to get address of callee function in a register in LowerCall()
682 RegsToPass.push_back(std::make_pair(VE::SX12, Callee)); in LowerCall()
713 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerCall()
731 SDValue StackPtr = DAG.getRegister(VE::SX11, PtrVT); in LowerCall()
838 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerCall()
860 // VE uses 64 bit addressing, so we need multiple instructions to generate in isOffsetFoldingLegal()
890 // It's fast anytime on VE in allowsMisalignedMemoryAccesses()
911 setStackPointerRegisterToSaveRestore(VE::SX11); in VETargetLowering()
921 // VE stores all argument by 8 bytes alignment in VETargetLowering()
1015 // Handle PIC mode first. VE needs a got load for every variable! in makeAddress()
1057 // The mappings for emitLeading/TrailingFence for VE is designed by following
1107 // VE uses Release consistency, so need a fence instruction if it is a in lowerATOMIC_FENCE()
1118 return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other, in lowerATOMIC_FENCE()
1124 return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other, in lowerATOMIC_FENCE()
1133 return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other, in lowerATOMIC_FENCE()
1292 Chain = DAG.getCopyFromReg(Chain, DL, VE::SX0, PtrVT, Chain.getValue(1)); in lowerToTLSGeneralDynamicModel()
1310 // code described in VE-tls_v1.1.pdf (*1) as its input. Instead, we always in lowerGlobalTLSAddress()
1313 // *1: https://www.nec.com/en/global/prod/hpc/aurora/document/VE-tls_v1.1.pdf in lowerGlobalTLSAddress()
1344 SDValue SubRegEven = DAG.getTargetConstant(VE::sub_even, DL, MVT::i32); in lowerLoadF128()
1345 SDValue SubRegOdd = DAG.getTargetConstant(VE::sub_odd, DL, MVT::i32); in lowerLoadF128()
1347 // VE stores Hi64 to 8(addr) and Lo64 to 0(addr) in lowerLoadF128()
1393 VM = DAG.getMachineNode(VE::LVMir_m, DL, MVT::i64, in lowerLoadI1()
1414 VM = DAG.getMachineNode(VE::LVMyir_y, DL, MVT::i64, in lowerLoadI1()
1456 SDValue SubRegEven = DAG.getTargetConstant(VE::sub_even, DL, MVT::i32); in lowerStoreF128()
1457 SDValue SubRegOdd = DAG.getTargetConstant(VE::sub_odd, DL, MVT::i32); in lowerStoreF128()
1468 // VE stores Hi64 to 8(addr) and Lo64 to 0(addr) in lowerStoreF128()
1507 DAG.getMachineNode(VE::SVMmi, DL, MVT::i64, StNode->getValue(), in lowerStoreI1()
1522 DAG.getMachineNode(VE::SVMyi, DL, MVT::i64, StNode->getValue(), in lowerStoreI1()
1576 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(VE::SX9, PtrVT), in lowerVASTART()
1597 // VE f128 values must be stored with 16 bytes alignment. We don't in lowerVAARG()
1963 /// JumpTable for VE.
1965 /// VE cannot generate relocatable symbol in jump table. VE cannot
2028 const TargetRegisterClass *RC = &VE::I64RegClass; in prepareMBB()
2038 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2042 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2045 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result) in prepareMBB()
2046 .addReg(VE::SX15) in prepareMBB()
2054 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2058 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2061 BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result) in prepareMBB()
2078 const TargetRegisterClass *RC = &VE::I64RegClass; in prepareSymbol()
2090 BuildMI(MBB, I, DL, TII->get(VE::GETFUNPLT), Result) in prepareSymbol()
2099 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2103 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2106 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result) in prepareSymbol()
2107 .addReg(VE::SX15) in prepareSymbol()
2119 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2123 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2126 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Tmp3) in prepareSymbol()
2127 .addReg(VE::SX15) in prepareSymbol()
2130 BuildMI(MBB, I, DL, TII->get(VE::LDrii), Result) in prepareSymbol()
2142 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2146 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2149 BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result) in prepareSymbol()
2169 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in setupEntryBlockForSjLj()
2241 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in emitEHSjLjSetJmp()
2245 MIB.addReg(VE::SX17); in emitEHSjLjSetJmp()
2250 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in emitEHSjLjSetJmp()
2261 BuildMI(*ThisMBB, MI, DL, TII->get(VE::EH_SjLj_Setup)).addMBB(RestoreMBB); in emitEHSjLjSetJmp()
2269 BuildMI(MainMBB, DL, TII->get(VE::LEAzii), MainDestReg) in emitEHSjLjSetJmp()
2276 BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(VE::PHI), DstReg) in emitEHSjLjSetJmp()
2288 BuildMI(RestoreMBB, DL, TII->get(VE::LDrii), VE::SX17); in emitEHSjLjSetJmp()
2289 MIB.addReg(VE::SX10); in emitEHSjLjSetJmp()
2294 BuildMI(RestoreMBB, DL, TII->get(VE::LEAzii), RestoreDestReg) in emitEHSjLjSetJmp()
2298 BuildMI(RestoreMBB, DL, TII->get(VE::BRCFLa_t)).addMBB(SinkMBB); in emitEHSjLjSetJmp()
2318 Register Tmp = MRI.createVirtualRegister(&VE::I64RegClass); in emitEHSjLjLongJmp()
2320 Register FP = VE::SX9; in emitEHSjLjLongJmp()
2321 Register SP = VE::SX11; in emitEHSjLjLongJmp()
2337 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), FP); in emitEHSjLjLongJmp()
2344 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), Tmp); in emitEHSjLjLongJmp()
2352 BuildMI(*ThisMBB, MI, DL, TII->get(VE::ORri), VE::SX10) in emitEHSjLjLongJmp()
2357 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), SP); in emitEHSjLjLongJmp()
2364 BuildMI(*ThisMBB, MI, DL, TII->get(VE::BCFLari_t)) in emitEHSjLjLongJmp()
2470 BuildMI(TrapBB, DL, TII->get(VE::BSICrii), VE::SX10) in emitSjLjDispatchBlock()
2487 BuildMI(DispatchBB, DL, TII->get(VE::NOP)) in emitSjLjDispatchBlock()
2493 BuildMI(DispatchBB, DL, TII->get(VE::GETGOT), VE::SX15); in emitSjLjDispatchBlock()
2497 const TargetRegisterClass *RC = &VE::I64RegClass; in emitSjLjDispatchBlock()
2499 addFrameReference(BuildMI(DispatchBB, DL, TII->get(VE::LDLZXrii), IReg), FI, in emitSjLjDispatchBlock()
2502 BuildMI(DispatchBB, DL, TII->get(VE::BRCFLir_t)) in emitSjLjDispatchBlock()
2510 BuildMI(DispatchBB, DL, TII->get(VE::LEAzii), TmpReg) in emitSjLjDispatchBlock()
2514 BuildMI(DispatchBB, DL, TII->get(VE::BRCFLrr_t)) in emitSjLjDispatchBlock()
2530 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1) in emitSjLjDispatchBlock()
2534 BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2) in emitSjLjDispatchBlock()
2537 BuildMI(DispContBB, DL, TII->get(VE::LEASLrri), BReg) in emitSjLjDispatchBlock()
2538 .addReg(VE::SX15) in emitSjLjDispatchBlock()
2546 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1) in emitSjLjDispatchBlock()
2550 BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2) in emitSjLjDispatchBlock()
2553 BuildMI(DispContBB, DL, TII->get(VE::LEASLrii), BReg) in emitSjLjDispatchBlock()
2569 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1) in emitSjLjDispatchBlock()
2572 BuildMI(DispContBB, DL, TII->get(VE::LDrri), TReg) in emitSjLjDispatchBlock()
2576 BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t)) in emitSjLjDispatchBlock()
2595 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1) in emitSjLjDispatchBlock()
2598 BuildMI(DispContBB, DL, TII->get(VE::LDLZXrri), OReg) in emitSjLjDispatchBlock()
2605 BuildMI(DispContBB, DL, TII->get(VE::ADDSLrr), TReg) in emitSjLjDispatchBlock()
2608 BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t)) in emitSjLjDispatchBlock()
2682 case VE::EH_SjLj_LongJmp: in EmitInstrWithCustomInserter()
2684 case VE::EH_SjLj_SetJmp: in EmitInstrWithCustomInserter()
2686 case VE::EH_SjLj_Setup_Dispatch: in EmitInstrWithCustomInserter()
2705 Val <<= 32; // Immediate value of float place at higher bits on VE. in isSimm7()
2755 // safe since VE uses f64 result of f128 comparison. in safeWithoutCompWithNull()
2807 // VE's condition move can handle MImm in True clause, so nothing to do. in combineSelect()
2809 // VE's condition move can handle MImm in True clause, so swap True and in combineSelect()
2863 // VE's comparison can handle MImm in RHS, so nothing to do. in combineSelectCC()
2865 // VE's comparison can handle Simm7 in LHS, so swap LHS and RHS, and in combineSelectCC()
2871 // VE's condition move can handle MImm in True clause, so nothing to do. in combineSelectCC()
2873 // VE's condition move can handle MImm in True clause, so swap True and in combineSelectCC()
3021 SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32); in combineTRUNCATE()
3044 // VE Inline Assembly Support
3070 RC = &VE::I64RegClass; in getRegForInlineAsmConstraint()
3073 RC = &VE::V64RegClass; in getRegForInlineAsmConstraint()
3083 // VE Target Optimization Support
3097 // VE doesn't have vector and not instruction. in hasAndNot()
3101 // VE allows different immediate values for X and Y where ~X & Y. in hasAndNot()
3102 // Only simm7 works for X, and only mimm works for Y on VE. However, this in hasAndNot()
3110 // correctly with Aurora VE. in hasAndNot()
3141 SDValue(DAG.getMachineNode(VE::LVSvr, DL, MVT::i64, {Vec, HalfIdx}), 0); in lowerEXTRACT_VECTOR_ELT()
3149 SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32); in lowerEXTRACT_VECTOR_ELT()
3199 SDValue(DAG.getMachineNode(VE::LVSvr, DL, MVT::i64, {Vec, HalfIdx}), 0); in lowerINSERT_VECTOR_ELT()
3210 SDValue(DAG.getMachineNode(VE::LSVrr_v, DL, Vec.getSimpleValueType(), in lowerINSERT_VECTOR_ELT()