Lines Matching refs:insn

11 multiclass SXU<SDPatternOperator operator, Instruction insn> {
13             (insn GR32:$src)>;
15             (insn (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
22                Instruction insn> {
24             (insn cls:$src1, GR32:$src2)>;
26             (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>;
31                Instruction insn> {
33             (insn cls:$src1, GR32:$src2)>;
35             (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>;
44            PatFrag imm, Instruction insn>
46         (insn mode:$addr, (UIMM8 imm:$src))>;
51                     Instruction insn> {
52   def : RMWI<z_anyextloadi8, operator, truncstorei8, mode, imm32, insn>;
53   def : RMWI<z_anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
58 multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
62             (insn cls:$src1, mode:$src2)>;
65             (insn cls:$src1, mode:$src2)>;
70 class StoreGR64<Instruction insn, SDPatternOperator operator,
73         (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), mode:$XBD2)>;
78 multiclass StoreGR64Pair<Instruction insn, Instruction insny,
80   def : StoreGR64<insn, operator, bdxaddr12pair>;
86 class StoreGR64PC<Instruction insn, SDPatternOperator operator>
88         (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), pcrel32:$XBD2)> {
99 multiclass CondStores64<Instruction insn, Instruction insninv,
105             (insn (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr,
117 multiclass MVCLoadStore<SDPatternOperator load, ValueType vt, Instruction insn,
120             (insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
128                            ValueType vt, Instruction insn, bits<5> length> {
130             (insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
149 multiclass CompareZeroFP<Instruction insn, RegisterOperand cls> {
150   def : Pat<(z_any_fcmp cls:$reg, (fpimm0)), (insn cls:$reg)>;
152   def : Pat<(z_any_fcmp cls:$reg, (fpimmneg0)), (insn cls:$reg)>;
157 class BinaryRRWithType<Instruction insn, RegisterOperand cls,
159   : Pat<(vt (operator cls:$x, cls:$y)), (insn cls:$x, cls:$y)>;
164 class FPConversion<Instruction insn, SDPatternOperator operator, TypedReg tr1,
167         (insn tr2.op:$vec, suppress, mode)>;
171 class FPMinMax<Instruction insn, SDPatternOperator operator, TypedReg tr,
174         (insn tr.op:$vec1, tr.op:$vec2, function)>;