Lines Matching +full:op +full:- +full:mode

1 //===-- SystemZPatterns.td - SystemZ-specific pattern rules ---*- tblgen-*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Record that INSN performs a 64-bit version of unary operator OPERATOR
10 // in which the operand is sign-extended from 32 to 64 bits.
18 // Record that INSN performs a 64-bit version of binary operator OPERATOR
20 // is sign-extended from a 32-bit register.
38 // Record that INSN performs a binary read-modify-write operation,
40 // respectively.  MODE is the addressing mode and IMM is the type
43            SDPatternOperator store, AddressingMode mode,
45   : Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr),
46         (insn mode:$addr, (UIMM8 imm:$src))>;
50 multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode,
52   def : RMWI<z_anyextloadi8, operator, truncstorei8, mode, imm32, insn>;
53   def : RMWI<z_anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
57 // The inserted operand is loaded using LOAD from an address of mode MODE.
59                      SDPatternOperator load, AddressingMode mode> {
61               cls:$src1, (load mode:$src2)),
62             (insn cls:$src1, mode:$src2)>;
64               (load mode:$src2), cls:$src1),
65             (insn cls:$src1, mode:$src2)>;
68 // INSN stores the low 32 bits of a GPR to a memory with addressing mode MODE.
71                 AddressingMode mode>
72   : Pat<(operator GR64:$R1, mode:$XBD2),
73         (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), mode:$XBD2)>;
84 // INSN stores the low 32 bits of a GPR using PC-relative addressing.
89   // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
101                         AddressingMode mode> {
102   def : Pat<(store (z_select_ccmask GR64:$new, (load mode:$addr),
104                    mode:$addr),
105             (insn (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr,
107   def : Pat<(store (z_select_ccmask (load mode:$addr), GR64:$new,
109                    mode:$addr),
110             (insninv (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr,
123 // Use NC-like instruction INSN for block_op operation OPERATOR.
163 // and 0 to allow them.  MODE is the rounding mode to use.
165                    TypedReg tr2, bits<3> suppress, bits<4> mode>
166   : Pat<(tr1.vt (operator (tr2.vt tr2.op:$vec))),
167         (insn tr2.op:$vec, suppress, mode)>;
173   : Pat<(tr.vt (operator (tr.vt tr.op:$vec1), (tr.vt tr.op:$vec2))),
174         (insn tr.op:$vec1, tr.op:$vec2, function)>;