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1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">;
10 def IsTargetELF : Predicate<"Subtarget->isTargetELF()">;
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
26 // has been made. Sets the output to the address of the dynamically-
49 //===----------------------------------------------------------------------===//
51 //===----------------------------------------------------------------------===//
56 // with the condition-code mask being the first operand. It seems friendlier
83 // Define AsmParser extended mnemonics for each general condition-code mask
84 // (integer or floating-point)
127 // Fused compare-and-branch instructions.
130 // We nevertheless pretend that the relative compare-and-branch
135 // their raw CRJ-like form, but use assembly macros like CRJE when writing
158 // Define AsmParser mnemonics for each integer condition-code mask.
222 //===----------------------------------------------------------------------===//
224 //===----------------------------------------------------------------------===//
234 // Fused compare-and-trap instructions.
236 // These patterns work the same way as for compare-and-branch.
271 //===----------------------------------------------------------------------===//
273 //===----------------------------------------------------------------------===//
276 // These instructions don't hard-code %r14 as the return address register.
395 //===----------------------------------------------------------------------===//
397 //===----------------------------------------------------------------------===//
404 // We don't define 32-bit Mux stores if we don't have STOCFH, because the
405 // low-only STOC should then always be used if possible.
431 //===----------------------------------------------------------------------===//
433 //===----------------------------------------------------------------------===//
449 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF,
456 // Other 16-bit immediates.
462 // 32-bit immediates.
534 // 8-bit immediate stores to 8-bit fields.
537 // 16-bit immediate stores to 16-, 32- or 64-bit fields.
542 // Memory-to-memory moves.
566 //===----------------------------------------------------------------------===//
568 //===----------------------------------------------------------------------===//
573 // Expands to SELR or SELFHR or a branch-and-move sequence,
581 // Define AsmParser extended mnemonics for each general condition-code mask.
604 // created by early if-conversion.
606 // Expands to LOCR or LOCFHR or a branch-and-move sequence,
622 // Define AsmParser extended mnemonics for each general condition-code mask.
639 // created by early if-conversion.
653 // Define AsmParser extended mnemonics for each general condition-code mask.
664 //===----------------------------------------------------------------------===//
666 //===----------------------------------------------------------------------===//
670 // either way, but signed-extending loads have a short LH and a long LHY,
671 // while zero-extending loads have only the long LLH.
673 //===----------------------------------------------------------------------===//
675 // 32-bit extensions from registers.
679 // 64-bit extensions from registers.
687 // Match 32-to-64-bit sign extensions in which the source is already
688 // in a 64-bit register.
692 // 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH,
700 // 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH,
709 // 64-bit extensions from memory.
718 //===----------------------------------------------------------------------===//
720 //===----------------------------------------------------------------------===//
722 // 32-bit extensions from registers.
733 // 64-bit extensions from registers.
738 // Match 32-to-64-bit zero extensions in which the source is already
739 // in a 64-bit register.
743 // 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH,
751 // 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH,
760 // 64-bit extensions from memory.
767 // 31-to-64-bit zero extensions.
792 //===----------------------------------------------------------------------===//
794 //===----------------------------------------------------------------------===//
796 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
804 //===----------------------------------------------------------------------===//
806 //===----------------------------------------------------------------------===//
808 // Truncations of 64-bit registers to 32-bit registers.
812 // Truncations of 32-bit registers to 8-bit memory. STCMux expands to
820 // Truncations of 32-bit registers to 16-bit memory. STHMux expands to
829 // Truncations of 64-bit registers to memory.
836 // Store characters under mask -- not (yet) used for codegen.
840 //===----------------------------------------------------------------------===//
841 // Multi-register moves
842 //===----------------------------------------------------------------------===//
844 // Multi-register loads.
850 // Multi-register stores.
855 //===----------------------------------------------------------------------===//
857 //===----------------------------------------------------------------------===//
859 // Byte-swapping register moves.
863 // Byte-swapping loads.
868 // Byte-swapping stores.
873 // Byte-swapping memory-to-memory moves.
877 //===----------------------------------------------------------------------===//
879 //===----------------------------------------------------------------------===//
881 // Load BDX-style addresses.
885 // Load a PC-relative address. There's no version of this instruction
886 // with a 16-bit offset, so there's no relaxation.
896 //===----------------------------------------------------------------------===//
898 //===----------------------------------------------------------------------===//
930 //===----------------------------------------------------------------------===//
932 //===----------------------------------------------------------------------===//
944 // Insert characters under mask -- not (yet) used for codegen.
950 // Insertions of a 16-bit immediate, leaving other bits unaffected.
968 // ...likewise for 32-bit immediates. For GR32s this is a general
969 // full-width move. (We use IILF rather than something like LLILF
970 // for 32-bit moves because IILF leaves the upper 32 bits of the
983 // a zero-extended value.
988 //===----------------------------------------------------------------------===//
990 //===----------------------------------------------------------------------===//
1007 // Addition of signed 16-bit immediates.
1012 // Addition of signed 32-bit immediates.
1049 // Addition of signed 16-bit immediates.
1055 // Addition of unsigned 32-bit immediates.
1059 // Addition of signed 32-bit immediates.
1090 //===----------------------------------------------------------------------===//
1092 //===----------------------------------------------------------------------===//
1157 // Subtraction of unsigned 32-bit immediates.
1194 //===----------------------------------------------------------------------===//
1196 //===----------------------------------------------------------------------===//
1206 // ANDs of a 16-bit immediate, leaving other bits unaffected.
1207 // The CC result only reflects the 16-bit field, not the full register.
1223 // ANDs of a 32-bit immediate, leaving other bits unaffected.
1224 // The CC result only reflects the 32-bit field, which means we can
1253 //===----------------------------------------------------------------------===//
1255 //===----------------------------------------------------------------------===//
1264 // ORs of a 16-bit immediate, leaving other bits unaffected.
1265 // The CC result only reflects the 16-bit field, not the full register.
1281 // ORs of a 32-bit immediate, leaving other bits unaffected.
1282 // The CC result only reflects the 32-bit field, which means we can
1310 //===----------------------------------------------------------------------===//
1312 //===----------------------------------------------------------------------===//
1321 // XORs of a 32-bit immediate, leaving other bits unaffected.
1322 // The CC result only reflects the 32-bit field, which means we can
1350 //===----------------------------------------------------------------------===//
1352 //===----------------------------------------------------------------------===//
1368 // NAND.
1370 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>;
1371 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>;
1391 //===----------------------------------------------------------------------===//
1393 //===----------------------------------------------------------------------===//
1397 // since they are three-operand instructions.
1412 // Multiplication of a signed 16-bit immediate.
1416 // Multiplication of a signed 32-bit immediate.
1459 //===----------------------------------------------------------------------===//
1461 //===----------------------------------------------------------------------===//
1498 //===----------------------------------------------------------------------===//
1500 //===----------------------------------------------------------------------===//
1531 // These can act like 32-bit operands provided that the constant start and
1569 //===----------------------------------------------------------------------===//
1571 //===----------------------------------------------------------------------===//
1588 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH,
1595 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH,
1620 // Comparison between memory and a signed 16-bit immediate.
1640 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI
1668 // Comparison between memory and an unsigned 8-bit immediate.
1671 // Comparison between memory and an unsigned 16-bit immediate.
1678 // Memory-to-memory comparison.
1713 // Compare logical characters under mask -- not (yet) used for codegen.
1719 //===----------------------------------------------------------------------===//
1721 //===----------------------------------------------------------------------===//
1737 //===----------------------------------------------------------------------===//
1739 //===----------------------------------------------------------------------===//
1833 //===----------------------------------------------------------------------===//
1835 //===----------------------------------------------------------------------===//
1874 //===----------------------------------------------------------------------===//
1875 // Message-security assist
1876 //===----------------------------------------------------------------------===//
1907 //===----------------------------------------------------------------------===//
1909 //===----------------------------------------------------------------------===//
1924 //===----------------------------------------------------------------------===//
1926 //===----------------------------------------------------------------------===//
1969 //===----------------------------------------------------------------------===//
1971 //===----------------------------------------------------------------------===//
1973 // Read a 32-bit access register into a GR32. As with all GR32 operations,
1975 // when a 64-bit address is stored in a pair of access registers.
1993 //===----------------------------------------------------------------------===//
1995 //===----------------------------------------------------------------------===//
2005 // Branch and link - like BAS, but also extracts CC and program mask.
2030 //===----------------------------------------------------------------------===//
2032 //===----------------------------------------------------------------------===//
2060 //===----------------------------------------------------------------------===//
2062 //===----------------------------------------------------------------------===//
2072 //===----------------------------------------------------------------------===//
2074 //===----------------------------------------------------------------------===//
2147 //===----------------------------------------------------------------------===//
2149 //===----------------------------------------------------------------------===//
2268 //===----------------------------------------------------------------------===//
2270 //===----------------------------------------------------------------------===//
2273 // equivalent to (and (xor x, -1), y)
2274 def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y),
2277 // Use LCGR/AGHI for i64 xor with -1.
2278 def : Pat<(xor GR64:$x, (i64 -1)),
2279 (AGHI (LCGR GR64:$x), (i64 -1))>;
2312 // Substitute (x*64-s) with (-s), since shift/rotate instructions only
2338 //===----------------------------------------------------------------------===//
2340 //===----------------------------------------------------------------------===//