Lines Matching refs:cond4
2320 : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
2322 [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> {
2340 : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
2358 : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
2384 (ins cond4:$valid, cond4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2410 : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1,
2437 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2464 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
2492 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
2519 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
2546 (ins cls:$R1, cls:$R2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2575 (ins cls:$R1, imm:$I2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2604 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, cond4:$M3),
2946 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
3118 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
3122 cond4:$valid, cond4:$M3))]> {
3550 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
3553 cond4:$valid, cond4:$M3))]> {
3596 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
3599 cond4:$valid, cond4:$M4))]> {
3663 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
3666 cond4:$valid, cond4:$M3))]> {
5196 (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> {
5236 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
5238 cond4:$valid, cond4:$M3))]> {
5253 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
5255 cond4:$valid, cond4:$M4))]> {
5267 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
5269 cond4:$valid, cond4:$M3))]> {
5281 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3),
5284 cond4:$valid, cond4:$R3))]> {
5301 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), []> {