Lines Matching refs:X2
633 bits<4> X2;
639 let Inst{19-16} = X2;
652 bits<4> X2;
658 let Inst{19-16} = X2;
671 bits<4> X2;
678 let Inst{35-32} = X2;
695 bits<4> X2;
701 let Inst{35-32} = X2;
717 bits<4> X2;
723 let Inst{35-32} = X2;
739 bits<4> X2;
745 let Inst{35-32} = X2;
1737 bits<4> X2;
1744 let Inst{35-32} = X2;
2315 : InstRXa<opcode, (outs), (ins GR64:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2384 (ins cond4:$valid, cond4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2391 (ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2396 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
2402 : InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
2411 (bdxaddr20only $B2, $D2, $X2):$XBD2),
2419 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
2426 : InstRXYb<opcode, (outs), (ins (bdxaddr20only $B2, $D2, $X2):$XBD2),
2659 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2667 (ins cls:$R1src, (bdxaddr20only $B2, $D2, $X2):$XBD2),
2763 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2775 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2799 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2809 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
2817 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2,
2822 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3029 : InstRXa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3035 : InstRXYa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3175 : InstRXa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3186 : InstRXE<opcode, (outs cls:$R1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3199 : InstRXYa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3293 : InstVRX<opcode, (outs tr.op:$V1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3303 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3311 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3315 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3322 : InstRXa<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3327 : InstRXYa<opcode, (outs), (ins cls:$R1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
3749 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
3763 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3780 (ins cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3793 (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
4107 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
4174 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
4240 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4252 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4266 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4409 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4613 (ins cls2:$R1src, cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4856 (ins tr2.op:$V1src, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
5054 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
5106 : Pseudo<(outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
5158 : Pseudo<(outs cls:$R1), (ins cls:$R2, (mode $B2, $D2, $X2):$XBD2), []> {
5181 (ins cls:$R2, cls:$R3, (mode $B2, $D2, $X2):$XBD2), []> {
5218 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
5310 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
5403 : Alias<6, (outs tr.op:$V1), (ins (mode $B2, $D2, $X2):$XBD2),
5409 : Alias<6, (outs), (ins tr.op:$V1, (mode $B2, $D2, $X2):$XBD2),