Lines Matching refs:V3
1188 bits<5> V3;
1194 let Inst{35-32} = V3{3-0};
1198 let Inst{10} = V3{4};
1210 bits<5> V3;
1217 let Inst{31-28} = V3{3-0};
1223 let Inst{9} = V3{4};
1258 bits<5> V3;
1265 let Inst{31-28} = V3{3-0};
1271 let Inst{9} = V3{4};
1379 bits<5> V3;
1386 let Inst{31-28} = V3{3-0};
1396 let Inst{9} = V3{4};
1408 bits<5> V3;
1416 let Inst{31-28} = V3{3-0};
1423 let Inst{9} = V3{4};
1438 bits<5> V3;
1446 let Inst{31-28} = V3{3-0};
1456 let Inst{9} = V3{4};
1468 bits<5> V3;
1476 let Inst{31-28} = V3{3-0};
1483 let Inst{9} = V3{4};
1577 bits<5> V3;
1583 let Inst{31-28} = V3{3-0};
1590 let Inst{9} = V3{4};
1627 bits<5> V3;
1632 let Inst{35-32} = V3{3-0};
1637 let Inst{10} = V3{4};
1672 bits<5> V3;
1677 let Inst{35-32} = V3{3-0};
1682 let Inst{10} = V3{4};
2738 def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2740 mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
2742 def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2744 mnemonic#"\t$V1, $V3, $BD2", []>;
2884 def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2887 mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
2889 def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2891 mnemonic#"\t$V1, $V3, $BD2", []>;
3868 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
3869 mnemonic#"\t$V1, $V3, $I2",
3870 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
3877 (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
3878 mnemonic#"\t$V1, $V3, $I2, $M4", []>;
3918 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3919 mnemonic#"\t$V1, $V2, $V3",
3921 (tr2.vt tr2.op:$V3)))]> {
3927 : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5),
3928 mnemonic#"\t$V1, $V2, $V3, $M5", []> {
3934 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3935 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3952 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3953 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
3967 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
3968 mnemonic#"\t$V1, $V2, $V3, $M5", []>;
3969 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
3970 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
3971 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
3973 tr2.op:$V3, 0)>;
3981 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3982 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3983 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3984 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3991 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3992 mnemonic#"\t$V1, $V2, $V3",
3994 (tr2.vt tr2.op:$V3)))]> {
4005 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
4006 mnemonic#"\t$V1, $V2, $V3, $M4", []> {
4013 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4014 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
4034 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4036 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
4057 (ins tr2.op:$V3, (shift12only $B2, $D2):$BD2),
4058 mnemonic#"\t$V1, $V3, $BD2",
4059 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
4066 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4:$M4),
4067 mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
4083 (ins tr.op:$V3, (shift12only $B2, $D2):$BD2),
4084 mnemonic#"\t$R1, $V3, $BD2",
4085 [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
4091 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4: $M4),
4092 mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
4638 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4639 mnemonic#"\t$V1, $V2, $V3, $I4",
4641 (tr2.vt tr2.op:$V3),
4672 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
4673 mnemonic#"\t$V1, $V2, $V3, $M5",
4675 (tr2.vt tr2.op:$V3),
4691 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
4693 tr2.op:$V3, 0)>;
4697 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
4699 tr2.op:$V3, 0)>;
4705 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4706 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
4707 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
4708 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4715 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
4716 mnemonic#"\t$V1, $V2, $V3, $M4",
4718 (tr2.vt tr2.op:$V3),
4728 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M6),
4729 mnemonic#"\t$V1, $V2, $V3, $M6",
4731 (tr2.vt tr2.op:$V3),
4739 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4741 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
4746 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4747 mnemonic#"\t$V1, $V2, $V3, $V4",
4749 (tr2.vt tr2.op:$V3),
4757 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
4758 mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> {
4769 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, imm32zx4:$M6),
4770 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", []>;
4771 def : Pat<(operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3),
4773 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, 0)>;
4774 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4776 tr2.op:$V3, tr1.op:$V4, 0)>;
4782 (ins VR128:$V2, VR128:$V3, VR128:$V4,
4784 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4785 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4786 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4794 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4795 mnemonic#"\t$V1, $V2, $V3, $V4",
4797 (tr2.vt tr2.op:$V3),
4807 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4808 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4830 VR128:$V3, imm32zx4:$M4),
4831 mnemonic#"\t$V1, $V2, $V3, $M4", []>;
4870 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4871 mnemonic#"\t$V1, $V2, $V3, $I4",
4874 (tr2.vt tr2.op:$V3),
4883 (ins VR128:$V1src, VR128:$V2, VR128:$V3,
4885 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
4892 (ins VR128:$V2, VR128:$V3,
4894 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []>;
4907 (ins tr2.op:$V2, tr3.op:$V3, tr4.op:$V4, m6mask:$M6),
4908 mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
4910 (tr3.vt tr3.op:$V3),
4919 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4920 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4933 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4935 tr2.op:$V3, tr2.op:$V4, 0)>;
4940 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
4942 tr2.op:$V3, tr2.op:$V4, 0)>;
4948 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4949 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,