Lines Matching refs:R3
182 // Assembly operands sometimes have a different order; in particular, R3 often
338 bits<4> R3;
343 let Inst{35-32} = R3;
355 bits<4> R3;
360 let Inst{35-32} = R3;
499 bits<4> R3;
505 let Inst{7-4} = R3;
530 bits<4> R3;
534 let Inst{15-12} = R3;
547 bits<4> R3;
551 let Inst{15-12} = R3;
694 bits<4> R3;
700 let Inst{39-36} = R3;
761 bits<4> R3;
767 let Inst{19-16} = R3;
795 bits<4> R3;
801 let Inst{35-32} = R3;
814 bits<4> R3;
819 let Inst{19-16} = R3;
867 bits<4> R3;
873 let Inst{35-32} = R3;
1041 bits<4> R3;
1045 let Inst{35-32} = R3;
1060 bits<4> R3;
1066 let Inst{35-32} = R3;
1118 bits<4> R3;
1121 let Inst{39-36} = R3;
1495 bits<4> R3;
1500 let Inst{31-28} = R3;
1650 bits<4> R3;
1655 let Inst{35-32} = R3;
1695 bits<4> R3;
1699 let Inst{35-32} = R3;
2674 : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2675 mnemonic#"\t$R1, $R3, $RI2", []> {
2682 (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2683 mnemonic#"\t$R1, $R3, $RI2", []> {
2690 (ins cls:$R1src, cls:$R3, (bdaddr12only $B2, $D2):$BD2),
2691 mnemonic#"\t$R1, $R3, $BD2", []> {
2699 (ins cls:$R1src, cls:$R3, (bdaddr20only $B2, $D2):$BD2),
2700 mnemonic#"\t$R1, $R3, $BD2", []> {
2707 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
2708 mnemonic#"\t$R1, $R3, $BD2", []> {
2714 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
2715 mnemonic#"\t$R1, $R3, $BD2", []> {
2730 : InstSSe<opcode, (outs cls:$R1, cls:$R3),
2732 mnemonic#"\t$R1, $R3, $BD2, $BD4", []> {
2830 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2831 mnemonic#"\t$V1, $R3, $BD2",
2832 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2841 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2842 mnemonic#"\t$V1, $R3, $BD2",
2843 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2860 : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
2861 mnemonic#"\t$R1, $R3, $BD2", []> {
2867 : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
2868 mnemonic#"\t$R1, $R3, $BD2", []> {
3349 let R3 = 0;
3452 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2),
3453 mnemonic#"\t$R1, $R3, $R2",
3454 [(set cls1:$R1, (operator cls2:$R3, cls2:$R2))]> {
3462 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3463 mnemonic#"\t$R1, $R2, $R3",
3464 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
3473 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls2:$R3),
3475 [(set cls1:$R1, (operator cls2:$R2, cls2:$R3))]> {
3476 let R3 = R2;
3510 : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3511 mnemonic#"\t$R1, $R3, $R2",
3512 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
3596 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
3597 mnemonic#"$M4\t$R1, $R2, $R3",
3598 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3,
3611 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2, imm32zx4:$M4),
3612 mnemonic#"\t$R1, $R2, $R3, $M4", []>;
3618 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2),
3619 mnemonic#V.suffix#"\t$R1, $R2, $R3", []> {
3644 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
3645 mnemonic#"\t$R1, $R3, $I2",
3646 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
3717 let R3 = 0;
3724 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (shift20only $B2, $D2):$BD2),
3725 mnemonic#"\t$R1, $R3, $BD2",
3726 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
3780 (ins cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3781 mnemonic#"\t$R1, $R3, $XBD2",
3782 [(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> {
3847 : InstSSF<opcode, (outs cls:$R3),
3849 mnemonic#"\t$R3, $BD1, $BD2", []> {
4040 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
4041 mnemonic#"\t$V1, $R2, $R3",
4042 [(set (tr.vt tr.op:$V1), (operator GR64:$R2, GR64:$R3))]>;
4072 (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
4073 mnemonic#"\t$V1, $R3, $BD2",
4074 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
4097 (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
4098 mnemonic#"\t$V1, $R3, $BD2",
4099 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
4185 (bdaddr12only $B2, $D2):$BD2, cls:$R3),
4186 mnemonic#"\t$RBD1, $BD2, $R3", []>;
4439 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4440 mnemonic#"\t$R1, $R2, $R3", []> {
4448 (ins cls1:$R1src, cls2:$R2src, cls3:$R3),
4449 mnemonic#"\t$R1, $R2, $R3", []> {
4458 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4459 mnemonic#"\t$R1, $R3, $R2", []> {
4467 : InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3),
4469 mnemonic#"\t$R1, $R3, $R2", []> {
4470 let Constraints = "$R1 = $R1src, $R2 = $R2src, $R3 = $R3src";
4509 (bdaddr12only $B2, $D2):$BD2, cls:$R3),
4510 mnemonic#"\t$BD1, $BD2, $R3", []>;
4515 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4),
4516 mnemonic#"\t$R1, $R2, $R3, $M4", []>;
4521 : InstRRFb<opcode, (outs cls1:$R1, cls3:$R3),
4523 mnemonic#"\t$R1, $R3, $R2, $M4", []> {
4536 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2),
4537 mnemonic#"\t$R1, $R3, $R2",
4538 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, cls2:$R2))]> {
4582 (ins cls1:$R1, cls2:$R3, (bdaddr12only $B2, $D2):$BD2),
4583 mnemonic#"\t$R1, $R3, $BD2", []>;
4588 (ins cls1:$R1, cls2:$R3, (bdaddr20only $B2, $D2):$BD2),
4589 mnemonic#"\t$R1, $R3, $BD2", []>;
4593 : InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
4595 mnemonic#"\t$R1, $R3, $BD2", []> {
4596 let Constraints = "$R1 = $R1src, $R3 = $R3src";
4602 : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
4604 mnemonic#"\t$R1, $R3, $BD2", []> {
4605 let Constraints = "$R1 = $R1src, $R3 = $R3src";
4613 (ins cls2:$R1src, cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4614 mnemonic#"\t$R1, $R3, $XBD2",
4615 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3,
4813 (ins tr2.op:$V1src, cls:$R3, (shift12only $B2, $D2):$BD2),
4814 mnemonic#"\t$V1, $R3, $BD2",
4816 cls:$R3,
4835 (ins VR128:$V1src, GR64:$R3, (shift12only $B2, $D2):$BD2,
4837 mnemonic#"\t$V1, $R3, $BD2, $M4", []> {
4956 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4957 mnemonic#"\t$R1, $R2, $R3, $M4", []>;
4971 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4972 mnemonic#"\t$R1, $R3, $R2, $M4", []>;
4985 (ins cls:$R1, (bdaddr12only $B2, $D2):$BD2, cls:$R3,
4987 mnemonic#"\t$R1, $BD2, $R3, $BD4", []>;
4991 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (mode $B2, $D2):$BD2),
4992 mnemonic#"\t$R1, $R3, $BD2",
4993 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
5011 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
5012 mnemonic#"\t$R1, $R3, $BD2",
5013 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
5023 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
5024 mnemonic#"\t$R1, $R3, $BD2",
5025 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
5136 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
5137 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
5181 (ins cls:$R2, cls:$R3, (mode $B2, $D2, $X2):$XBD2), []> {
5253 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
5254 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3,
5281 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3),
5284 cond4:$valid, cond4:$R3))]> {
5301 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), []> {
5430 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;