Lines Matching refs:R2
301 bits<4> R2;
307 let Inst{35-32} = R2;
373 bits<4> R2;
380 let Inst{35-32} = R2;
486 bits<4> R2;
490 let Inst{3-0} = R2;
500 bits<4> R2;
506 let Inst{3-0} = R2;
515 bits<4> R2;
520 let Inst{3-0} = R2;
529 bits<4> R2;
537 let Inst{3-0} = R2;
546 bits<4> R2;
554 let Inst{3-0} = R2;
563 bits<4> R2;
570 let Inst{3-0} = R2;
579 bits<4> R2;
586 let Inst{3-0} = R2;
595 bits<4> R2;
603 let Inst{3-0} = R2;
612 bits<4> R2;
619 let Inst{35-32} = R2;
1324 bits<4> R2;
1330 let Inst{35-32} = R2;
1494 bits<4> R2;
1499 let Inst{35-32} = R2;
2263 let R2 = 0;
2267 : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
2268 mnemonic#"\t$R1, $R2", []>;
2297 let R2 = 0;
2311 : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2),
2312 mnemonic#"\t$R1, $R2", []>;
2358 : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
2359 !subst("#", "${R1}", mnemonic)#"\t$R2", []> {
2364 : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
2365 mnemonic#"\t$R1, $R2", []>;
2368 : InstRR<opcode, (outs), (ins GR64:$R2),
2369 mnemonic#"\t$R2", []> {
2375 : InstRR<opcode, (outs), (ins ADDR64:$R2),
2376 !subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
2464 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
2465 mnemonic#"$M3\t$R1, $R2, $RI4", []>;
2470 (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
2471 mnemonic#"\t$R1, $R2, $M3, $RI4", []>;
2475 : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
2476 mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> {
2519 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
2520 mnemonic#"$M3\t$R1, $R2", []>;
2524 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
2525 mnemonic#"\t$R1, $R2, $M3", []>;
2536 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
2537 mnemonic#V.suffix#"\t$R1, $R2", []> {
2546 (ins cls:$R1, cls:$R2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2547 mnemonic#"$M3\t$R1, $R2, $BD4", []>;
2552 (ins cls:$R1, cls:$R2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
2553 mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
2558 (ins cls:$R1, cls:$R2, (bdaddr12only $B4, $D4):$BD4),
2559 mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
2644 : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2645 mnemonic#"\t$R1, $R2", []> {
2651 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2652 mnemonic#"\t$R1, $R2", []> {
2992 let R2 = 0;
2999 let R2 = 0;
3057 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
3058 mnemonic#"\t$R1, $R2",
3059 [(set cls1:$R1, (operator cls2:$R2))]> {
3066 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
3067 mnemonic#"\t$R1, $R2",
3068 [(set cls1:$R1, (operator cls2:$R2))]> {
3078 let R2 = 0;
3083 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src),
3084 mnemonic#"\t$R1, $R2", []> {
3342 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3343 mnemonic#"\t$R1, $R2", []>;
3347 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3348 mnemonic#"\t$R1, $R2", []> {
3355 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3356 mnemonic#"\t$R1, $R2", []> {
3397 : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3398 mnemonic#"\t$R1, $R2", []> {
3399 let Constraints = "$R1 = $R1src, $R2 = $R2src";
3405 : InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src),
3406 mnemonic#"\t$R1, $R2", []> {
3407 let Constraints = "$R2 = $R2src";
3413 : InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3414 mnemonic#"\t$R1, $R2", []> {
3415 let Constraints = "$R1 = $R1src, $R2 = $R2src";
3421 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3422 mnemonic#"\t$R1, $R2", []> {
3423 let Constraints = "$R1 = $R1src, $R2 = $R2src";
3430 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3431 mnemonic#"\t$R1, $R2",
3432 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
3441 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3442 mnemonic#"\t$R1, $R2",
3443 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
3452 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2),
3453 mnemonic#"\t$R1, $R3, $R2",
3454 [(set cls1:$R1, (operator cls2:$R3, cls2:$R2))]> {
3462 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3463 mnemonic#"\t$R1, $R2, $R3",
3464 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
3473 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls2:$R3),
3474 mnemonic#"\t$R1, $R2",
3475 [(set cls1:$R1, (operator cls2:$R2, cls2:$R3))]> {
3476 let R3 = R2;
3510 : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3511 mnemonic#"\t$R1, $R3, $R2",
3512 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
3518 : InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M3),
3519 mnemonic#"\t$R1, $R2, $M3", []>;
3523 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
3524 mnemonic#"\t$R1, $R2, $M3", []> {
3537 : InstRRFd<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M4),
3538 mnemonic#"\t$R1, $R2, $M4", []>;
3542 : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
3543 mnemonic#"\t$R1, $M3, $R2", []> {
3550 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
3551 mnemonic#"$M3\t$R1, $R2",
3552 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
3568 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
3569 mnemonic#"\t$R1, $R2, $M3", []> {
3577 : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3578 mnemonic#V.suffix#"\t$R1, $R2", []> {
3596 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
3597 mnemonic#"$M4\t$R1, $R2, $R3",
3598 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3,
3611 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2, imm32zx4:$M4),
3612 mnemonic#"\t$R1, $R2, $R3, $M4", []>;
3618 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2),
3619 mnemonic#V.suffix#"\t$R1, $R2, $R3", []> {
4040 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
4041 mnemonic#"\t$V1, $R2, $R3",
4042 [(set (tr.vt tr.op:$V1), (operator GR64:$R2, GR64:$R3))]>;
4190 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
4191 mnemonic#"\t$R1, $R2",
4192 [(set CC, (operator cls1:$R1, cls2:$R2))]> {
4200 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
4201 mnemonic#"\t$R1, $R2",
4202 [(set CC, (operator cls1:$R1, cls2:$R2))]> {
4439 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4440 mnemonic#"\t$R1, $R2, $R3", []> {
4447 : InstRRFa<opcode, (outs cls1:$R1, cls2:$R2),
4449 mnemonic#"\t$R1, $R2, $R3", []> {
4450 let Constraints = "$R1 = $R1src, $R2 = $R2src";
4458 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4459 mnemonic#"\t$R1, $R3, $R2", []> {
4467 : InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3),
4469 mnemonic#"\t$R1, $R3, $R2", []> {
4470 let Constraints = "$R1 = $R1src, $R2 = $R2src, $R3 = $R3src";
4478 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
4479 mnemonic#"\t$R1, $R2, $M3", []>;
4491 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2),
4493 mnemonic#"\t$R1, $R2, $M3", []> {
4494 let Constraints = "$R1 = $R1src, $R2 = $R2src";
4515 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4),
4516 mnemonic#"\t$R1, $R2, $R3, $M4", []>;
4522 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M4),
4523 mnemonic#"\t$R1, $R3, $R2, $M4", []> {
4531 (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
4532 mnemonic#"\t$R1, $M3, $R2, $M4", []>;
4536 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2),
4537 mnemonic#"\t$R1, $R3, $R2",
4538 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, cls2:$R2))]> {
4648 (ins cls:$R2, imm32zx8:$I3, imm32zx4:$M4),
4649 mnemonic#"\t$V1, $R2, $I3, $M4", []>;
4956 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4957 mnemonic#"\t$R1, $R2, $R3, $M4", []>;
4971 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4972 mnemonic#"\t$R1, $R3, $R2, $M4", []>;
5000 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
5001 mnemonic#"\t$R1, $R2", []> {
5045 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
5047 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", [], I3Or, I4Or> {
5119 : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
5120 [(set cls1:$R1, (operator cls2:$R2))]> {
5158 : Pseudo<(outs cls:$R1), (ins cls:$R2, (mode $B2, $D2, $X2):$XBD2), []> {
5181 (ins cls:$R2, cls:$R3, (mode $B2, $D2, $X2):$XBD2), []> {
5196 (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> {
5236 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
5237 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
5253 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
5254 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3,
5322 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
5430 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
5443 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,