Lines Matching full:m3
284 bits<4> M3;
290 let Inst{15-12} = M3;
302 bits<4> M3;
309 let Inst{15-12} = M3;
321 bits<4> M3;
326 let Inst{35-32} = M3;
407 bits<4> M3;
412 let Inst{35-32} = M3;
467 bits<4> M3;
473 let Inst{35-32} = M3;
564 bits<4> M3;
567 let Inst{15-12} = M3;
596 bits<4> M3;
600 let Inst{15-12} = M3;
613 bits<4> M3;
622 let Inst{15-12} = M3;
674 bits<4> M3;
681 let Inst{15-12} = M3;
778 bits<4> M3;
784 let Inst{19-16} = M3;
850 bits<4> M3;
857 let Inst{11-8} = M3;
888 bits<4> M3;
894 let Inst{35-32} = M3;
1149 bits<4> M3;
1155 let Inst{15-12} = M3;
1349 bits<4> M3;
1362 let Inst{15-12} = M3;
1531 bits<4> M3;
1538 let Inst{23-20} = M3;
1554 bits<4> M3;
1561 let Inst{23-20} = M3;
1602 bits<4> M3;
1609 let Inst{23-20} = M3;
1717 bits<4> M3;
1724 let Inst{15-12} = M3;
1740 bits<4> M3;
1747 let Inst{15-12} = M3;
1887 let M3 = 0;
2273 let M3 = 0;
2437 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2438 mnemonic#"$M3\t$R1, $I2", []>;
2442 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
2443 mnemonic#"\t$R1, $I2, $M3", []>;
2451 let M3 = V.ccmask;
2464 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
2465 mnemonic#"$M3\t$R1, $R2, $RI4", []>;
2470 (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
2471 mnemonic#"\t$R1, $R2, $M3, $RI4", []>;
2479 let M3 = V.ccmask;
2492 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
2493 mnemonic#"$M3\t$R1, $I2, $RI4", []>;
2498 (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
2499 mnemonic#"\t$R1, $I2, $M3, $RI4", []>;
2507 let M3 = V.ccmask;
2519 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
2520 mnemonic#"$M3\t$R1, $R2", []>;
2524 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
2525 mnemonic#"\t$R1, $R2, $M3", []>;
2540 let M3 = V.ccmask;
2546 (ins cls:$R1, cls:$R2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2547 mnemonic#"$M3\t$R1, $R2, $BD4", []>;
2552 (ins cls:$R1, cls:$R2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
2553 mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
2562 let M3 = V.ccmask;
2575 (ins cls:$R1, imm:$I2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2576 mnemonic#"$M3\t$R1, $I2, $BD4", []>;
2581 (ins cls:$R1, imm:$I2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
2582 mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
2591 let M3 = V.ccmask;
2604 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, cond4:$M3),
2605 mnemonic#"$M3\t$R1, $BD2", []>;
2610 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
2611 mnemonic#"\t$R1, $M3, $BD2", []>;
2626 let M3 = V.ccmask;
2802 let M3 = type;
2809 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
2810 mnemonic#"\t$V1, $XBD2, $M3", []> {
2818 imm32zx4:$M3),
2819 mnemonic#"\t$V1, $XBD2, $M3", []>;
2820 let M3 = 0 in
2946 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
2947 mnemonic#"$M3\t$R1, $BD2", []> {
2958 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2, imm32zx4:$M3),
2959 mnemonic#"\t$R1, $BD2, $M3", []> {
2974 let M3 = V.ccmask;
3087 let M3 = 0;
3118 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
3119 mnemonic#"$M3\t$R1, $BD2",
3122 cond4:$valid, cond4:$M3))]> {
3140 (ins cls:$R1src, (mode $B2, $D2):$BD2, imm32zx4:$M3),
3141 mnemonic#"\t$R1, $BD2, $M3", []> {
3160 let M3 = V.ccmask;
3193 let M3 = 0;
3225 let M3 = type;
3229 : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
3230 mnemonic#"\t$V1, $I2, $M3", []>;
3238 let M3 = type;
3247 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3248 mnemonic#"\t$V1, $V2, $M3", []> {
3255 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
3256 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
3268 let M3 = type, M4 = 0 in
3284 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
3285 mnemonic#"\t$V1, $V2, $M3, $M5", []>;
3286 def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
3288 imm32zx4:$M3, 0)>;
3296 let M3 = type;
3303 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3304 mnemonic#"\t$V1, $XBD2, $M3", []> {
3311 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3312 mnemonic#"\t$V1, $XBD2, $M3", []>;
3313 let M3 = 0 in
3357 let M3 = 0;
3425 let M3 = 0;
3518 : InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M3),
3519 mnemonic#"\t$R1, $R2, $M3", []>;
3523 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
3524 mnemonic#"\t$R1, $R2, $M3", []> {
3542 : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
3543 mnemonic#"\t$R1, $M3, $R2", []> {
3550 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
3551 mnemonic#"$M3\t$R1, $R2",
3553 cond4:$valid, cond4:$M3))]> {
3568 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
3569 mnemonic#"\t$R1, $R2, $M3", []> {
3583 let M3 = V.ccmask;
3663 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
3664 mnemonic#"$M3\t$R1, $I2",
3666 cond4:$valid, cond4:$M3))]> {
3677 (ins cls:$R1src, imm:$I2, imm32zx4:$M3),
3678 mnemonic#"\t$R1, $I2, $M3", []> {
3692 let M3 = V.ccmask;
3741 (ins (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
3742 mnemonic#"\t$R1, $BDL2, $M3", []> {
3773 let M3 = 0;
3906 let M3 = type;
3912 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3913 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
4045 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
4046 mnemonic#"\t$R1, $V2, $M3", []> {
4051 : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
4052 mnemonic#"\t$V1, $V2, $M3", []>;
4107 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
4108 mnemonic#"\t$V1, $XBD2, $M3",
4110 imm32zx4_timm:$M3))]> {
4117 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4118 mnemonic#"\t$R1, $M3, $BD2", []> {
4125 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4126 mnemonic#"\t$R1, $M3, $BD2", []> {
4146 imm32zx4:$M3),
4147 mnemonic#"\t$R1, $BDL2, $M3", []> {
4164 (ins VR128:$V1, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4165 mnemonic#"\t$V1, $VBD2, $M3", []> {
4174 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
4175 mnemonic#"\t$V1, $XBD2, $M3",
4176 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
4260 let M3 = 0;
4291 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4292 mnemonic#"\t$R1, $M3, $BD2", []> {
4299 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4300 mnemonic#"\t$R1, $M3, $BD2", []> {
4371 let M3 = type;
4379 : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4380 mnemonic#"\t$V1, $V2, $M3", []> {
4388 (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4),
4389 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
4395 : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4396 mnemonic#"\t$V1, $V2, $M3", []> {
4412 let M3 = 0;
4478 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
4479 mnemonic#"\t$R1, $R2, $M3", []>;
4492 (ins cls1:$R1src, cls2:$R2src, imm:$M3),
4493 mnemonic#"\t$R1, $R2, $M3", []> {
4531 (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
4532 mnemonic#"\t$R1, $M3, $R2, $M4", []>;
4548 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4549 mnemonic#"\t$R1, $M3, $BD2", []> {
4560 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4561 mnemonic#"\t$R1, $M3, $BD2", []> {
4627 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
4628 mnemonic#"\t$V1, $I2, $M3",
4630 imm:$I2, index:$M3))]> {
4660 let M3 = type;
4665 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
4666 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
4825 imm32zx4:$M3, imm32zx4:$M4),
4826 mnemonic#"\t$R1, $V2, $M3, $M4", []>;
4845 (ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4846 mnemonic#"\t$V1, $VBD2, $M3", []> {
4856 (ins tr2.op:$V1src, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
4857 mnemonic#"\t$V1, $XBD2, $M3",
4860 index:$M3))]> {
5196 (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> {
5236 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
5238 cond4:$valid, cond4:$M3))]> {
5267 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
5269 cond4:$valid, cond4:$M3))]> {