Lines Matching full:b2
634 bits<4> B2;
640 let Inst{15-12} = B2;
653 bits<4> B2;
659 let Inst{15-12} = B2;
672 bits<4> B2;
679 let Inst{31-28} = B2;
696 bits<4> B2;
702 let Inst{31-28} = B2;
718 bits<4> B2;
724 let Inst{31-28} = B2;
740 bits<4> B2;
746 let Inst{31-28} = B2;
762 bits<4> B2;
768 let Inst{15-12} = B2;
779 bits<4> B2;
785 let Inst{15-12} = B2;
796 bits<4> B2;
802 let Inst{31-28} = B2;
847 bits<4> B2;
854 let Inst{31-28} = B2;
868 bits<4> B2;
874 let Inst{31-28} = B2;
889 bits<4> B2;
895 let Inst{31-28} = B2;
978 bits<4> B2;
985 let Inst{15-12} = B2;
997 bits<4> B2;
1006 let Inst{15-12} = B2;
1018 bits<4> B2;
1027 let Inst{15-12} = B2;
1039 bits<4> B2;
1048 let Inst{15-12} = B2;
1058 bits<4> B2;
1067 let Inst{31-28} = B2;
1080 bits<4> B2;
1088 let Inst{15-12} = B2;
1099 bits<4> B2;
1105 let Inst{15-12} = B2;
1116 bits<4> B2;
1125 let Inst{15-12} = B2;
1134 bits<4> B2;
1138 let Inst{15-12} = B2;
1625 bits<4> B2;
1633 let Inst{31-28} = B2;
1648 bits<4> B2;
1656 let Inst{31-28} = B2;
1670 bits<4> B2;
1678 let Inst{31-28} = B2;
1693 bits<4> B2;
1700 let Inst{31-28} = B2;
1715 bits<4> B2;
1722 let Inst{31-28} = B2;
1738 bits<4> B2;
1745 let Inst{31-28} = B2;
1759 bits<4> B2;
1765 let Inst{31-28} = B2;
2278 : InstS<opcode, (outs), (ins (bdaddr12only $B2, $D2):$BD2),
2290 let B2 = 0;
2315 : InstRXa<opcode, (outs), (ins GR64:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2384 (ins cond4:$valid, cond4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2391 (ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2396 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
2402 : InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
2411 (bdxaddr20only $B2, $D2, $X2):$XBD2),
2419 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
2426 : InstRXYb<opcode, (outs), (ins (bdxaddr20only $B2, $D2, $X2):$XBD2),
2604 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, cond4:$M3),
2610 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
2622 : InstRSYb<opcode, (outs), (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2),
2659 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2667 (ins cls:$R1src, (bdxaddr20only $B2, $D2, $X2):$XBD2),
2690 (ins cls:$R1src, cls:$R3, (bdaddr12only $B2, $D2):$BD2),
2699 (ins cls:$R1src, cls:$R3, (bdaddr20only $B2, $D2):$BD2),
2707 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
2714 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
2731 (ins (bdaddr12only $B2, $D2):$BD2, (bdaddr12only $B4, $D4):$BD4),
2739 (ins (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
2743 (ins (bdaddr12only $B2, $D2):$BD2),
2763 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2775 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2799 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2809 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
2817 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2,
2822 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2830 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2841 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2851 (ins VR128:$V1, (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
2860 : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
2867 : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
2885 (bdaddr12only $B2, $D2):$BD2,
2890 (bdaddr12only $B2, $D2):$BD2),
2937 (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2),
2946 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
2958 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2, imm32zx4:$M3),
2968 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2),
3005 : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2),
3024 : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2),
3029 : InstRXa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3035 : InstRXYa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3118 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
3140 (ins cls:$R1src, (mode $B2, $D2):$BD2, imm32zx4:$M3),
3152 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2):$BD2),
3175 : InstRXa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3186 : InstRXE<opcode, (outs cls:$R1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3199 : InstRXYa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3293 : InstVRX<opcode, (outs tr.op:$V1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3303 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3311 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3315 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3322 : InstRXa<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3327 : InstRXYa<opcode, (outs), (ins cls:$R1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
3376 (bdaddr12only $B2, $D2):$BD2),
3382 (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
3387 (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
3392 (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2),
3714 (ins cls:$R1src, (shift12only $B2, $D2):$BD2),
3724 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (shift20only $B2, $D2):$BD2),
3741 (ins (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
3749 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
3763 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3780 (ins cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3793 (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
3848 (ins (bdaddr12pair $B1, $D1):$BD1, (bdaddr12pair $B2, $D2):$BD2),
4057 (ins tr2.op:$V3, (shift12only $B2, $D2):$BD2),
4066 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4:$M4),
4072 (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
4083 (ins tr.op:$V3, (shift12only $B2, $D2):$BD2),
4091 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4: $M4),
4097 (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
4107 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
4117 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4125 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4145 (ins cls:$R1, (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2,
4154 (ins (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
4164 (ins VR128:$V1, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4174 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
4185 (bdaddr12only $B2, $D2):$BD2, cls:$R3),
4240 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4252 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4266 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4291 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4299 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4318 (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
4403 let B2 = 0;
4409 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4433 (shift12only $B2, $D2):$BD2, imm32zx4:$I3),
4509 (bdaddr12only $B2, $D2):$BD2, cls:$R3),
4548 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4560 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4582 (ins cls1:$R1, cls2:$R3, (bdaddr12only $B2, $D2):$BD2),
4588 (ins cls1:$R1, cls2:$R3, (bdaddr20only $B2, $D2):$BD2),
4594 (ins cls1:$R1src, cls2:$R3src, (shift12only $B2, $D2):$BD2),
4603 (ins cls1:$R1src, cls2:$R3src, (shift20only $B2, $D2):$BD2),
4613 (ins cls2:$R1src, cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4813 (ins tr2.op:$V1src, cls:$R3, (shift12only $B2, $D2):$BD2),
4835 (ins VR128:$V1src, GR64:$R3, (shift12only $B2, $D2):$BD2,
4845 (ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4856 (ins tr2.op:$V1src, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
4985 (ins cls:$R1, (bdaddr12only $B2, $D2):$BD2, cls:$R3,
4991 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (mode $B2, $D2):$BD2),
5011 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
5023 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
5054 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
5106 : Pseudo<(outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
5158 : Pseudo<(outs cls:$R1), (ins cls:$R2, (mode $B2, $D2, $X2):$XBD2), []> {
5181 (ins cls:$R2, cls:$R3, (mode $B2, $D2, $X2):$XBD2), []> {
5196 (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> {
5218 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
5281 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3),
5301 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), []> {
5310 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
5403 : Alias<6, (outs tr.op:$V1), (ins (mode $B2, $D2, $X2):$XBD2),
5409 : Alias<6, (outs), (ins tr.op:$V1, (mode $B2, $D2, $X2):$XBD2),