Lines Matching refs:NegBitShift
4560 SDValue &NegBitShift) { in getCSAddressAndShifts() argument
4576 NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT, in getCSAddressAndShifts()
4608 SDValue AlignedAddr, BitShift, NegBitShift; in lowerATOMIC_LOAD_OP() local
4609 getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift); in lowerATOMIC_LOAD_OP()
4626 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
4704 SDValue AlignedAddr, BitShift, NegBitShift; in lowerATOMIC_CMP_SWAP() local
4705 getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift); in lowerATOMIC_CMP_SWAP()
4710 NegBitShift, DAG.getConstant(BitSize, DL, WideVT) }; in lowerATOMIC_CMP_SWAP()
8566 Register NegBitShift = MI.getOperand(5).getReg(); in emitAtomicLoadBinary() local
8628 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0); in emitAtomicLoadBinary()
8661 Register NegBitShift = MI.getOperand(5).getReg(); in emitAtomicLoadMinMax() local
8732 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0); in emitAtomicLoadMinMax()
8763 Register NegBitShift = MI.getOperand(6).getReg(); in emitAtomicCmpSwapW() local
8843 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize); in emitAtomicCmpSwapW()