Lines Matching +full:current +full:- +full:rotate
1 //===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "systemz-isel"
24 #define PASS_NAME "SystemZ DAG->DAG Pattern Instruction Selection"
47 // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it.
79 Base.getNode()->dump(DAG); in dump()
86 Index.getNode()->dump(DAG); in dump()
103 return (uint64_t(1) << Count) - 1; in allOnes()
106 // Represents operands 2 to 5 of the ROTATE AND ... SELECTED BITS operation
108 // Rotate (I5). The combined operand value is effectively:
110 // (or (rotl Input, Rotate), ~Mask)
114 // (and (rotl Input, Rotate), Mask)
122 Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63), in RxSBGOperands()
123 Rotate(0) {} in RxSBGOperands()
131 unsigned Rotate; member
139 return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0)); in getImm()
147 return Subtarget->getInstrInfo(); in getInstrInfo()
182 // PC-relative address matching routines used by SystemZOperands.td.
263 // Try to match Addr as an address with a base, 12-bit displacement
325 // using block (SS-format) instructions.
329 // non-overlapping case. We also need to avoid full overlap (i.e. two
339 // if A[1 - I] == X and if N can use a block operation like NC from A[I]
344 // requirements for a PC-relative access.
366 if (F.getFnAttribute("fentry-call").getValueAsString() != "true") { in runOnMachineFunction()
367 if (F.hasFnAttribute("mnop-mcount")) in runOnMachineFunction()
368 report_fatal_error("mnop-mcount only supported with fentry-call"); in runOnMachineFunction()
369 if (F.hasFnAttribute("mrecord-mcount")) in runOnMachineFunction()
370 report_fatal_error("mrecord-mcount only supported with fentry-call"); in runOnMachineFunction()
483 // Look through no-op truncations. in expandAddress()
488 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) { in expandAddress()
492 unsigned Op0Code = Op0->getOpcode(); in expandAddress()
493 unsigned Op1Code = Op1->getOpcode(); in expandAddress()
502 cast<ConstantSDNode>(Op0)->getSExtValue()); in expandAddress()
505 cast<ConstantSDNode>(Op1)->getSExtValue()); in expandAddress()
514 uint64_t Offset = (cast<GlobalAddressSDNode>(Full)->getOffset() - in expandAddress()
515 cast<GlobalAddressSDNode>(Anchor)->getOffset()); in expandAddress()
551 if (Base->getOpcode() == ISD::FrameIndex) in shouldUseLA()
574 // once. It should be a natural two-operand addition in that case. in shouldUseLA()
575 if (Index->hasOneUse()) in shouldUseLA()
578 // Prefer addition if the second operation is sign-extended, in the in shouldUseLA()
580 unsigned IndexOpcode = Index->getOpcode(); in shouldUseLA()
586 // Don't use LA for two-operand addition if either operand is only in shouldUseLA()
588 if (Base->hasOneUse()) in shouldUseLA()
604 cast<ConstantSDNode>(Addr)->getSExtValue())) in selectAddress()
639 if (N->getNodeId() == -1 || in insertDAGNode()
642 DAG->RepositionNode(Pos->getIterator(), N.getNode()); in insertDAGNode()
645 // Conservatively mark it with the same -abs(Id) to assure node id in insertDAGNode()
647 N->setNodeId(Pos->getNodeId()); in insertDAGNode()
658 Base = CurDAG->getRegister(0, VT); in getAddressOperands()
661 int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex(); in getAddressOperands()
662 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT); in getAddressOperands()
668 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); in getAddressOperands()
674 Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(Base), VT); in getAddressOperands()
686 Index = CurDAG->getRegister(0, VT); in getAddressOperands()
732 Index = Regs[1 - I]; in selectBDVAddr12Only()
760 uint64_t AndMask = MaskNode->getZExtValue(); in detectOrAndInsertion()
768 KnownBits Known = CurDAG->computeKnownBits(Op.getOperand(0)); in detectOrAndInsertion()
780 if (RxSBG.Rotate != 0) in refineRxSBGMask()
781 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)); in refineRxSBGMask()
783 if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) { in refineRxSBGMask()
792 // Rotate the mask in the same way as RxSBG.Input is rotated. in maskMatters()
793 if (RxSBG.Rotate != 0) in maskMatters()
794 Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate))); in maskMatters()
823 uint64_t Mask = MaskNode->getZExtValue(); in expandRxSBG()
828 KnownBits Known = CurDAG->computeKnownBits(Input); in expandRxSBG()
846 uint64_t Mask = ~MaskNode->getZExtValue(); in expandRxSBG()
851 KnownBits Known = CurDAG->computeKnownBits(Input); in expandRxSBG()
861 // Any 64-bit rotate left can be merged into the RxSBG. in expandRxSBG()
868 RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63; in expandRxSBG()
874 // Bits above the extended operand are don't-care. in expandRxSBG()
891 // Check that the extension bits are don't-care (i.e. are masked out in expandRxSBG()
895 if (maskMatters(RxSBG, allOnes(BitSize) - allOnes(InnerBitSize))) { in expandRxSBG()
896 // In the case where only the sign bit is active, increase Rotate with in expandRxSBG()
898 if (RxSBG.Mask == 1 && RxSBG.Rotate == 1) in expandRxSBG()
899 RxSBG.Rotate += (BitSize - InnerBitSize); in expandRxSBG()
913 uint64_t Count = CountNode->getZExtValue(); in expandRxSBG()
919 // Treat (shl X, count) as (rotl X, size-count) as long as the bottom in expandRxSBG()
925 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count) << Count)) in expandRxSBG()
929 RxSBG.Rotate = (RxSBG.Rotate + Count) & 63; in expandRxSBG()
940 uint64_t Count = CountNode->getZExtValue(); in expandRxSBG()
946 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top in expandRxSBG()
948 if (maskMatters(RxSBG, allOnes(Count) << (BitSize - Count))) in expandRxSBG()
951 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count), in expandRxSBG()
953 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count))) in expandRxSBG()
957 RxSBG.Rotate = (RxSBG.Rotate - Count) & 63; in expandRxSBG()
967 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT); in getUNDEF()
974 return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32, in convertTo()
977 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N); in convertTo()
984 EVT VT = N->getValueType(0); in tryRISBGZero()
1001 if (Count == 1 && N->getOpcode() != ISD::AND) in tryRISBGZero()
1006 // these ANDs into an RISBG later if a three-address instruction is useful. in tryRISBGZero()
1007 if (RISBG.Rotate == 0) { in tryRISBGZero()
1009 // Prefer AND for any 32-bit and-immediate operation. in tryRISBGZero()
1012 // As well as for any 64-bit operation that can be implemented via LLC(R), in tryRISBGZero()
1013 // LLH(R), LLGT(R), or one of the and-immediate instructions. in tryRISBGZero()
1023 if (Load->getMemoryVT() == MVT::i32 && in tryRISBGZero()
1024 (Load->getExtensionType() == ISD::EXTLOAD || in tryRISBGZero()
1025 Load->getExtensionType() == ISD::ZEXTLOAD) && in tryRISBGZero()
1027 Subtarget->hasLoadAndZeroRightmostByte()) in tryRISBGZero()
1031 // Replace the current node with an AND. Note that the current node in tryRISBGZero()
1035 SDValue Mask = CurDAG->getConstant(RISBG.Mask, DL, VT); in tryRISBGZero()
1036 SDValue New = CurDAG->getNode(ISD::AND, DL, VT, In, Mask); in tryRISBGZero()
1044 if (!N->isMachineOpcode()) in tryRISBGZero()
1052 if (Subtarget->hasMiscellaneousExtensions()) in tryRISBGZero()
1055 if (VT == MVT::i32 && Subtarget->hasHighWord() && in tryRISBGZero()
1056 // We can only use the 32-bit instructions if all source bits are in tryRISBGZero()
1061 ((RISBG.Start + RISBG.Rotate) & 63) >= 32 && in tryRISBGZero()
1062 ((RISBG.End + RISBG.Rotate) & 63) >= in tryRISBGZero()
1063 ((RISBG.Start + RISBG.Rotate) & 63)) { in tryRISBGZero()
1072 CurDAG->getTargetConstant(RISBG.Start, DL, MVT::i32), in tryRISBGZero()
1073 CurDAG->getTargetConstant(RISBG.End | 128, DL, MVT::i32), in tryRISBGZero()
1074 CurDAG->getTargetConstant(RISBG.Rotate, DL, MVT::i32) in tryRISBGZero()
1077 DL, VT, SDValue(CurDAG->getMachineNode(Opcode, DL, OpcodeVT, Ops), 0)); in tryRISBGZero()
1084 EVT VT = N->getValueType(0); in tryRxSBG()
1090 RxSBGOperands(Opcode, N->getOperand(0)), in tryRxSBG()
1091 RxSBGOperands(Opcode, N->getOperand(1)) in tryRxSBG()
1095 while (RxSBG[I].Input->hasOneUse() && expandRxSBG(RxSBG[I])) in tryRxSBG()
1112 SDValue Op0 = N->getOperand(I ^ 1); in tryRxSBG()
1117 if (Load->getMemoryVT() == MVT::i8) in tryRxSBG()
1125 if (Subtarget->hasMiscellaneousExtensions()) in tryRxSBG()
1132 CurDAG->getTargetConstant(RxSBG[I].Start, DL, MVT::i32), in tryRxSBG()
1133 CurDAG->getTargetConstant(RxSBG[I].End, DL, MVT::i32), in tryRxSBG()
1134 CurDAG->getTargetConstant(RxSBG[I].Rotate, DL, MVT::i32) in tryRxSBG()
1137 DL, VT, SDValue(CurDAG->getMachineNode(Opcode, DL, MVT::i64, Ops), 0)); in tryRxSBG()
1145 EVT VT = Node->getValueType(0); in splitLargeImmediate()
1147 SDValue Upper = CurDAG->getConstant(UpperVal, DL, VT); in splitLargeImmediate()
1149 Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper); in splitLargeImmediate()
1169 SDValue Lower = CurDAG->getConstant(LowerVal, DL, VT); in splitLargeImmediate()
1170 SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower); in splitLargeImmediate()
1184 EVT VT = Node->getValueType(0); in loadVectorConstant()
1188 Ops.push_back(CurDAG->getTargetConstant(OpVal, DL, MVT::i32)); in loadVectorConstant()
1189 SDValue Op = CurDAG->getNode(VCI.Opcode, DL, VCI.VecVT, Ops); in loadVectorConstant()
1194 SDValue BitCast = CurDAG->getNode(ISD::BITCAST, DL, VT, Op); in loadVectorConstant()
1201 Node, CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, Op).getNode()); in loadVectorConstant()
1210 SDValue CP = CurDAG->getTargetConstantPool( in loadPoolVectorConstant()
1211 ConstantInt::get(Type::getInt128Ty(*CurDAG->getContext()), Val), in loadPoolVectorConstant()
1212 TLI->getPointerTy(CurDAG->getDataLayout())); in loadPoolVectorConstant()
1216 SDValue(CurDAG->getMachineNode(SystemZ::LARL, DL, PtrVT, CP), 0), in loadPoolVectorConstant()
1217 CurDAG->getTargetConstant(0, DL, PtrVT), in loadPoolVectorConstant()
1218 CurDAG->getRegister(0, PtrVT), in loadPoolVectorConstant()
1219 CurDAG->getEntryNode() in loadPoolVectorConstant()
1221 ResNode = CurDAG->getMachineNode(SystemZ::VL, DL, VT, MVT::Other, Ops); in loadPoolVectorConstant()
1226 MachineFunction& MF = CurDAG->getMachineFunction(); in loadPoolVectorConstant()
1231 CurDAG->setNodeMemRefs(cast<MachineSDNode>(ResNode), {MemOp}); in loadPoolVectorConstant()
1236 SDValue ElemV = N->getOperand(2); in tryGather()
1241 unsigned Elem = ElemN->getZExtValue(); in tryGather()
1242 EVT VT = N->getValueType(0); in tryGather()
1246 auto *Load = dyn_cast<LoadSDNode>(N->getOperand(1)); in tryGather()
1247 if (!Load || !Load->hasNUsesOfValue(1, 0)) in tryGather()
1249 if (Load->getMemoryVT().getSizeInBits() != in tryGather()
1250 Load->getValueType(0).getSizeInBits()) in tryGather()
1254 if (!selectBDVAddr12Only(Load->getBasePtr(), ElemV, Base, Disp, Index) || in tryGather()
1260 N->getOperand(0), Base, Disp, Index, in tryGather()
1261 CurDAG->getTargetConstant(Elem, DL, MVT::i32), Load->getChain() in tryGather()
1263 SDNode *Res = CurDAG->getMachineNode(Opcode, DL, VT, MVT::Other, Ops); in tryGather()
1270 SDValue Value = Store->getValue(); in tryScatter()
1273 if (Store->getMemoryVT().getSizeInBits() != Value.getValueSizeInBits()) in tryScatter()
1283 unsigned Elem = ElemN->getZExtValue(); in tryScatter()
1288 if (!selectBDVAddr12Only(Store->getBasePtr(), ElemV, Base, Disp, Index) || in tryScatter()
1294 Vec, Base, Disp, Index, CurDAG->getTargetConstant(Elem, DL, MVT::i32), in tryScatter()
1295 Store->getChain() in tryScatter()
1297 ReplaceNode(Store, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops)); in tryScatter()
1312 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) in isFusableLoadOpStorePattern()
1315 // Is the store non-extending and non-indexed? in isFusableLoadOpStorePattern()
1316 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal()) in isFusableLoadOpStorePattern()
1319 SDValue Load = StoredVal->getOperand(0); in isFusableLoadOpStorePattern()
1320 // Is the stored value a non-extending and non-indexed load? in isFusableLoadOpStorePattern()
1332 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() || in isFusableLoadOpStorePattern()
1333 LoadNode->getOffset() != StoreNode->getOffset()) in isFusableLoadOpStorePattern()
1338 SDValue Chain = StoreNode->getChain(); in isFusableLoadOpStorePattern()
1343 InputChain = LoadNode->getChain(); in isFusableLoadOpStorePattern()
1363 for (SDValue Op : StoredVal->ops()) in isFusableLoadOpStorePattern()
1374 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), in isFusableLoadOpStorePattern()
1394 SDValue StoredVal = StoreNode->getOperand(1); in tryFoldLoadStoreIntoMemOperand()
1395 unsigned Opc = StoredVal->getOpcode(); in tryFoldLoadStoreIntoMemOperand()
1401 EVT MemVT = StoreNode->getMemoryVT(); in tryFoldLoadStoreIntoMemOperand()
1441 auto OperandV = OperandC->getAPIntValue(); in tryFoldLoadStoreIntoMemOperand()
1443 OperandV = -OperandV; in tryFoldLoadStoreIntoMemOperand()
1446 Operand = CurDAG->getTargetConstant(OperandV, DL, MemVT); in tryFoldLoadStoreIntoMemOperand()
1449 if (!selectBDAddr20Only(StoreNode->getBasePtr(), Base, Disp)) in tryFoldLoadStoreIntoMemOperand()
1454 CurDAG->getMachineNode(NewOpc, DL, MVT::i32, MVT::Other, Ops); in tryFoldLoadStoreIntoMemOperand()
1455 CurDAG->setNodeMemRefs( in tryFoldLoadStoreIntoMemOperand()
1456 Result, {StoreNode->getMemOperand(), LoadNode->getMemOperand()}); in tryFoldLoadStoreIntoMemOperand()
1460 CurDAG->RemoveDeadNode(Node); in tryFoldLoadStoreIntoMemOperand()
1467 if (Load->getMemoryVT() != Store->getMemoryVT()) in canUseBlockOperation()
1471 if (Load->isVolatile() || Store->isVolatile()) in canUseBlockOperation()
1475 if (Load->isInvariant() && Load->isDereferenceable()) in canUseBlockOperation()
1479 const Value *V1 = Load->getMemOperand()->getValue(); in canUseBlockOperation()
1480 const Value *V2 = Store->getMemOperand()->getValue(); in canUseBlockOperation()
1485 uint64_t Size = Load->getMemoryVT().getStoreSize(); in canUseBlockOperation()
1486 int64_t End1 = Load->getSrcValueOffset() + Size; in canUseBlockOperation()
1487 int64_t End2 = Store->getSrcValueOffset() + Size; in canUseBlockOperation()
1491 return AA->isNoAlias(MemoryLocation(V1, End1, Load->getAAInfo()), in canUseBlockOperation()
1492 MemoryLocation(V2, End2, Store->getAAInfo())); in canUseBlockOperation()
1497 auto *Load = cast<LoadSDNode>(Store->getValue()); in storeLoadCanUseMVC()
1501 uint64_t Size = Load->getMemoryVT().getStoreSize(); in storeLoadCanUseMVC()
1504 if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode())) in storeLoadCanUseMVC()
1507 if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode())) in storeLoadCanUseMVC()
1517 auto *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I)); in storeLoadCanUseBlockBinary()
1518 auto *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I)); in storeLoadCanUseBlockBinary()
1519 return !LoadA->isVolatile() && LoadA->getMemoryVT() == LoadB->getMemoryVT() && in storeLoadCanUseBlockBinary()
1527 TypeSize StoreSize = MemAccess->getMemoryVT().getStoreSize(); in storeLoadIsAligned()
1528 SDValue BasePtr = MemAccess->getBasePtr(); in storeLoadIsAligned()
1529 MachineMemOperand *MMO = MemAccess->getMemOperand(); in storeLoadIsAligned()
1534 if (MemAccess->getAlign().value() < StoreSize || in storeLoadIsAligned()
1535 (LdSt && !LdSt->getOffset().isUndef())) in storeLoadIsAligned()
1539 if (MMO->getOffset() % StoreSize != 0) in storeLoadIsAligned()
1543 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) in storeLoadIsAligned()
1544 if ((PSV->isGOT() || PSV->isConstantPool())) in storeLoadIsAligned()
1552 if (GA->getOffset() % StoreSize != 0) in storeLoadIsAligned()
1556 const GlobalValue *GV = GA->getGlobal(); in storeLoadIsAligned()
1557 const DataLayout &DL = GV->getDataLayout(); in storeLoadIsAligned()
1558 if (GV->getPointerAlignment(DL).value() < StoreSize) in storeLoadIsAligned()
1568 ETy = L->getExtensionType(); in getLoadExtType()
1570 ETy = AL->getExtensionType(); in getLoadExtType()
1578 if (Node->isMachineOpcode()) { in Select()
1579 LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); in Select()
1580 Node->setNodeId(-1); in Select()
1584 unsigned Opcode = Node->getOpcode(); in Select()
1587 if (Node->getOperand(1).getOpcode() != ISD::Constant) in Select()
1593 if (Node->getOperand(1).getOpcode() != ISD::Constant) in Select()
1598 // If this is a 64-bit operation in which both 32-bit halves are nonzero, in Select()
1601 if (Node->getValueType(0) == MVT::i64 && in Select()
1602 Node->getOperand(0).getOpcode() != ISD::Constant) in Select()
1603 if (auto *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) { in Select()
1604 uint64_t Val = Op1->getZExtValue(); in Select()
1606 // logical operations provided by miscellaneous-extensions-3. in Select()
1607 if (Subtarget->hasMiscellaneousExtensions3()) { in Select()
1608 unsigned ChildOpcode = Node->getOperand(0).getOpcode(); in Select()
1610 if (Val == (uint64_t)-1 && Opcode == ISD::XOR) in Select()
1614 // Check whether this expression matches OR-with-complement in Select()
1617 auto Op0 = Node->getOperand(0); in Select()
1618 if (auto *Op0Op1 = dyn_cast<ConstantSDNode>(Op0->getOperand(1))) in Select()
1619 if (Op0Op1->getZExtValue() == (uint64_t)-1) in Select()
1623 // Don't split an XOR with -1 as LCGR/AGHI is more compact. in Select()
1624 if (Opcode == ISD::XOR && Op1->isAllOnes()) in Select()
1627 splitLargeImmediate(Opcode, Node, Node->getOperand(0), in Select()
1628 Val - uint32_t(Val), uint32_t(Val)); in Select()
1635 if (Node->getOperand(1).getOpcode() != ISD::Constant) in Select()
1648 if (Node->getValueType(0) == MVT::i128) { in Select()
1650 SDValue Src = Node->getOperand(0); in Select()
1651 Src = CurDAG->getNode(ISD::BITCAST, DL, MVT::v16i8, Src); in Select()
1656 SDValue Res = SDValue(CurDAG->getMachineNode(SystemZ::VPERM, DL, in Select()
1659 Res = CurDAG->getNode(ISD::BITCAST, DL, MVT::i128, Res); in Select()
1669 // If this is a 64-bit constant that is out of the range of LLILF, in Select()
1670 // LLIHF and LGFI, split it into two 32-bit pieces. in Select()
1671 if (Node->getValueType(0) == MVT::i64) { in Select()
1672 uint64_t Val = Node->getAsZExtVal(); in Select()
1674 splitLargeImmediate(ISD::OR, Node, SDValue(), Val - uint32_t(Val), in Select()
1679 if (Node->getValueType(0) == MVT::i128) { in Select()
1680 const APInt &Val = Node->getAsAPIntVal(); in Select()
1694 SDValue Op0 = Node->getOperand(0); in Select()
1695 SDValue Op1 = Node->getOperand(1); in Select()
1699 (Subtarget->hasLoadStoreOnCond2() && in Select()
1700 Node->getValueType(0).isInteger() && in Select()
1701 Node->getValueType(0).getSizeInBits() <= 64 && in Select()
1703 isInt<16>(cast<ConstantSDNode>(Op1)->getSExtValue()) && in Select()
1705 isInt<16>(cast<ConstantSDNode>(Op0)->getSExtValue())))) { in Select()
1706 SDValue CCValid = Node->getOperand(2); in Select()
1707 SDValue CCMask = Node->getOperand(3); in Select()
1708 uint64_t ConstCCValid = CCValid.getNode()->getAsZExtVal(); in Select()
1709 uint64_t ConstCCMask = CCMask.getNode()->getAsZExtVal(); in Select()
1711 CCMask = CurDAG->getTargetConstant(ConstCCValid ^ ConstCCMask, in Select()
1713 SDValue Op4 = Node->getOperand(4); in Select()
1715 CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); in Select()
1726 EVT VT = Node->getValueType(0); in Select()
1749 APFloat Imm = cast<ConstantFPSDNode>(Node)->getValueAPF(); in Select()
1763 unsigned ElemBitSize = Store->getValue().getValueSizeInBits(); in Select()
1779 StoreSDNode *St = cast<StoreSDNode>(CurDAG->getTruncStore( in Select()
1780 AtomOp->getChain(), SDLoc(AtomOp), AtomOp->getVal(), in Select()
1781 AtomOp->getBasePtr(), AtomOp->getMemoryVT(), AtomOp->getMemOperand())); in Select()
1782 assert(St->getMemOperand()->isAtomic() && "Broken MMO."); in Select()
1786 if (AtomOp->getSuccessOrdering() == AtomicOrdering::SequentiallyConsistent) in Select()
1787 Chain = CurDAG->getMachineNode(SystemZ::Serialize, SDLoc(AtomOp), in Select()
1843 Subtarget->getRegisterInfo()->getPointerRegClass(*MF); in SelectInlineAsmMemoryOperand()
1845 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32); in SelectInlineAsmMemoryOperand()
1852 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, in SelectInlineAsmMemoryOperand()
1860 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, in SelectInlineAsmMemoryOperand()
1874 // IsProfitableToFold - Returns true if is profitable to fold the specific
1881 if (N.getOpcode() == ISD::LOAD && U->getOpcode() == SystemZISD::ICMP) { in IsProfitableToFold()
1882 if (!N.hasOneUse() || !U->hasOneUse()) in IsProfitableToFold()
1889 SDNode *CCUser = *U->use_begin(); in IsProfitableToFold()
1891 if (CCUser->getOpcode() == ISD::CopyToReg || in IsProfitableToFold()
1892 cast<RegisterSDNode>(CCUser->getOperand(1))->getReg() == SystemZ::CC) { in IsProfitableToFold()
1893 for (auto *U : CCUser->uses()) { in IsProfitableToFold()
1905 if (CCRegUser->isMachineOpcode() && in IsProfitableToFold()
1906 CCRegUser->getMachineOpcode() == SystemZ::BRC) in IsProfitableToFold()
1907 return !N->isPredecessorOf(CCUser->getOperand(0).getNode()); in IsProfitableToFold()
1947 // 0/-1 value, so it has priority over the other tests below. in getIPMConversion()
1953 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31); in getIPMConversion()
1955 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31); in getIPMConversion()
1959 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31); in getIPMConversion()
1961 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31); in getIPMConversion()
1965 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31); in getIPMConversion()
1970 return IPMConversion(-1, 0, SystemZ::IPM_CC); in getIPMConversion()
1972 // Handle cases where adding a value forces a non-sign bit to contain in getIPMConversion()
1977 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1); in getIPMConversion()
1981 // sign-based extractions above. in getIPMConversion()
1983 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31); in getIPMConversion()
1986 TopBit - (3 << SystemZ::IPM_CC), 31); in getIPMConversion()
1990 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31); in getIPMConversion()
1995 TopBit - (1 << SystemZ::IPM_CC), 31); in getIPMConversion()
2001 auto *TrueOp = dyn_cast<ConstantSDNode>(Node->getOperand(0)); in expandSelectBoolean()
2002 auto *FalseOp = dyn_cast<ConstantSDNode>(Node->getOperand(1)); in expandSelectBoolean()
2005 if (FalseOp->getZExtValue() != 0) in expandSelectBoolean()
2007 if (TrueOp->getSExtValue() != 1 && TrueOp->getSExtValue() != -1) in expandSelectBoolean()
2010 auto *CCValidOp = dyn_cast<ConstantSDNode>(Node->getOperand(2)); in expandSelectBoolean()
2011 auto *CCMaskOp = dyn_cast<ConstantSDNode>(Node->getOperand(3)); in expandSelectBoolean()
2014 int CCValid = CCValidOp->getZExtValue(); in expandSelectBoolean()
2015 int CCMask = CCMaskOp->getZExtValue(); in expandSelectBoolean()
2018 SDValue CCReg = Node->getOperand(4); in expandSelectBoolean()
2020 SDValue Result = CurDAG->getNode(SystemZISD::IPM, DL, MVT::i32, CCReg); in expandSelectBoolean()
2023 Result = CurDAG->getNode(ISD::XOR, DL, MVT::i32, Result, in expandSelectBoolean()
2024 CurDAG->getConstant(IPM.XORValue, DL, MVT::i32)); in expandSelectBoolean()
2027 Result = CurDAG->getNode(ISD::ADD, DL, MVT::i32, Result, in expandSelectBoolean()
2028 CurDAG->getConstant(IPM.AddValue, DL, MVT::i32)); in expandSelectBoolean()
2030 EVT VT = Node->getValueType(0); in expandSelectBoolean()
2032 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean()
2033 Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, in expandSelectBoolean()
2034 CurDAG->getConstant(IPM.Bit, DL, MVT::i32)); in expandSelectBoolean()
2037 Result = CurDAG->getNode(ISD::ANY_EXTEND, DL, VT, Result); in expandSelectBoolean()
2039 if (TrueOp->getSExtValue() == 1) { in expandSelectBoolean()
2041 Result = CurDAG->getNode(ISD::SRL, DL, VT, Result, in expandSelectBoolean()
2042 CurDAG->getConstant(IPM.Bit, DL, MVT::i32)); in expandSelectBoolean()
2043 Result = CurDAG->getNode(ISD::AND, DL, VT, Result, in expandSelectBoolean()
2044 CurDAG->getConstant(1, DL, VT)); in expandSelectBoolean()
2046 // Sign-extend from IPM.Bit using a pair of shifts. in expandSelectBoolean()
2047 int ShlAmt = VT.getSizeInBits() - 1 - IPM.Bit; in expandSelectBoolean()
2048 int SraAmt = VT.getSizeInBits() - 1; in expandSelectBoolean()
2049 Result = CurDAG->getNode(ISD::SHL, DL, VT, Result, in expandSelectBoolean()
2050 CurDAG->getConstant(ShlAmt, DL, MVT::i32)); in expandSelectBoolean()
2051 Result = CurDAG->getNode(ISD::SRA, DL, VT, Result, in expandSelectBoolean()
2052 CurDAG->getConstant(SraAmt, DL, MVT::i32)); in expandSelectBoolean()
2060 EVT VT = N->getValueType(0); in shouldSelectForReassoc()
2062 return N->getFlags().hasAllowReassociation() && in shouldSelectForReassoc()
2063 N->getFlags().hasNoSignedZeros() && Subtarget->hasVector() && in shouldSelectForReassoc()
2064 (VT != MVT::f32 || Subtarget->hasVectorEnhancements1()) && in shouldSelectForReassoc()
2065 !N->isStrictFPOpcode(); in shouldSelectForReassoc()
2071 if (Subtarget->hasLoadStoreOnCond2()) in PreprocessISelDAG()
2076 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), in PreprocessISelDAG()
2077 E = CurDAG->allnodes_end(); in PreprocessISelDAG()
2080 if (N->use_empty()) in PreprocessISelDAG()
2084 switch (N->getOpcode()) { in PreprocessISelDAG()
2093 LLVM_DEBUG(N->dump(CurDAG)); in PreprocessISelDAG()
2095 LLVM_DEBUG(Res.getNode()->dump(CurDAG)); in PreprocessISelDAG()
2098 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res); in PreprocessISelDAG()
2104 CurDAG->RemoveDeadNodes(); in PreprocessISelDAG()