Lines Matching refs:MemKind
122 unsigned MemKind : 4; member
189 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, in createMem() argument
193 Op->Mem.MemKind = MemKind; in createMem()
198 if (MemKind == BDLMem) in createMem()
200 if (MemKind == BDRMem) in createMem()
261 bool isMem(MemoryKind MemKind) const { in isMem()
263 (Mem.MemKind == MemKind || in isMem()
266 (Mem.MemKind == BDMem && MemKind == BDXMem))); in isMem()
268 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem() argument
269 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
271 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp12() argument
272 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff, true); in isMemDisp12()
274 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { in isMemDisp20() argument
275 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287, true); in isMemDisp20()
436 ParseStatus parseAddress(OperandVector &Operands, MemoryKind MemKind,
742 if (Op.MemKind == BDLMem) in print()
744 else if (Op.MemKind == BDRMem) in print()
1098 MemoryKind MemKind, in parseAddress() argument
1107 bool HasLength = (MemKind == BDLMem) ? true : false; in parseAddress()
1108 bool HasVectorIndex = (MemKind == BDVMem) ? true : false; in parseAddress()
1120 switch (MemKind) { in parseAddress()
1193 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp, in parseAddress()