47   // Alignments for 64 bit integers.  in computeDataLayout()
48   Ret += "-i64:64";  in computeDataLayout()
50   // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.  in computeDataLayout()
51   // On SparcV9 registers can hold 64 or 32 bits, on others only 32.  in computeDataLayout()
53     Ret += "-n32:64";  in computeDataLayout()
55     Ret += "-f128:64-n32";  in computeDataLayout()
69 // Code models. Some only make sense for 64-bit code.
99                                        StringRef CPU, StringRef FS,  in SparcTargetMachine()  argument
105     : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,  in SparcTargetMachine()
126   std::string FS =  in getSubtargetImpl()  local
135     FS += FS.empty() ? "+soft-float" : ",+soft-float";  in getSubtargetImpl()
137   auto &I = SubtargetMap[CPU + FS];  in getSubtargetImpl()
143     I = std::make_unique<SparcSubtarget>(CPU, TuneCPU, FS, *this,  in getSubtargetImpl()
201                                            StringRef CPU, StringRef FS,  in SparcV8TargetMachine()  argument
206     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}  in SparcV8TargetMachine()
211                                            StringRef CPU, StringRef FS,  in SparcV9TargetMachine()  argument
216     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}  in SparcV9TargetMachine()
221                                            StringRef CPU, StringRef FS,  in SparcelTargetMachine()  argument
226     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}  in SparcelTargetMachine()