Lines Matching refs:SP
34 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}
56 Reserved.set(SP::G1);
60 Reserved.set(SP::G2);
61 Reserved.set(SP::G3);
62 Reserved.set(SP::G4);
66 Reserved.set(SP::G5);
68 Reserved.set(SP::O6);
69 Reserved.set(SP::I6);
70 Reserved.set(SP::I7);
71 Reserved.set(SP::G0);
72 Reserved.set(SP::G6);
73 Reserved.set(SP::G7);
77 Reserved.set(SP::G0_G1);
79 Reserved.set(SP::G2_G3);
81 Reserved.set(SP::G4_G5);
83 Reserved.set(SP::O6_O7);
84 Reserved.set(SP::I6_I7);
85 Reserved.set(SP::G6_G7);
90 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
97 Reserved.set(SP::ASR1 + n);
99 for (TargetRegisterClass::iterator i = SP::IntRegsRegClass.begin();
100 i != SP::IntRegsRegClass.end(); ++i) {
118 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
142 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
147 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
150 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
160 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
162 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
163 .addReg(SP::G1).addImm(LOX10(Offset));
165 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
168 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
193 if (MI.getOpcode() == SP::STQFri) {
196 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
197 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
199 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
202 MI.setDesc(TII.get(SP::STDFri));
205 } else if (MI.getOpcode() == SP::LDQFri) {
208 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64);
209 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64);
211 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
215 MI.setDesc(TII.get(SP::LDDFri));
227 return SP::I6;
243 // If there's a reserved call frame, we can use SP to access locals.