Lines Matching refs:IntRegs
423 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
427 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
472 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
474 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
476 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
480 def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd),
563 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
584 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
606 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
625 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
626 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
627 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>;
628 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
629 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>;
675 (outs IntRegs:$rd),
683 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>;
684 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
685 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>;
745 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, IntRegs:$val),
749 (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr, IntRegs:$val),
753 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi, IntRegs:$val),
758 (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr, IntRegs:$val),
766 (outs IntRegs:$rd), (ins i32imm:$imm22),
777 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
780 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
784 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
787 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
790 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
794 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
796 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
799 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
803 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
806 def : Pat<(and IntRegs:$rs1, SETHIimm_not:$rs2),
809 def : Pat<(or IntRegs:$rs1, SETHIimm_not:$rs2),
822 defm SLL : F3_S<"sll", 0b100101, 0, shl, i32, shift_imm5, IntRegs>;
823 defm SRL : F3_S<"srl", 0b100110, 0, srl, i32, shift_imm5, IntRegs>;
824 defm SRA : F3_S<"sra", 0b100111, 0, sra, i32, shift_imm5, IntRegs>;
827 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
830 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
836 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
839 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
841 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
844 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
854 defm UMUL : F3_12<"umul", 0b001010, umullohi, IntRegs, i32, simm13Op, IIC_iu_umul>;
855 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>;
1060 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
1065 (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
1111 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
1115 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
1122 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
1126 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
1144 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
1151 (outs IntRegs:$rd), (ins),
1156 (outs IntRegs:$rd), (ins),
1161 (outs IntRegs:$rd), (ins),
1167 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1170 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1177 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1180 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1186 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1189 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1195 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1198 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1472 (outs IntRegs:$rd),
1473 (ins IntRegs:$rs1, IntRegs:$rs2, TailRelocSymTLSAdd:$sym),
1480 (outs IntRegs:$rd),
1534 : F4_1<0b101100, (outs IntRegs:$rd),
1535 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1540 : F4_2<0b101100, (outs IntRegs:$rd),
1541 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1549 : F4_1<0b101100, (outs IntRegs:$rd),
1550 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1554 : F4_2<0b101100, (outs IntRegs:$rd),
1555 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1659 : F4_1<0b101100, (outs IntRegs:$rd),
1660 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1663 : F4_2<0b101100, (outs IntRegs:$rd),
1664 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1687 (outs IntRegs:$rd), (ins IntRegs:$rs2),
1704 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1705 IntRegs:$swap, ASITag:$asi),
1712 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1713 IntRegs:$swap),
1720 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1725 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1730 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1735 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1744 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1747 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1800 (outs IntRegs:$rd), (ins PRRegs:$rs1),
1809 (outs IntRegs:$rd), (ins),
1816 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1819 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1929 def : Pat<(build_vector (i32 0), (i32 IntRegs:$a2)),
1932 (i32 IntRegs:$a2), sub_odd)>;
1941 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
1943 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
1944 (i32 IntRegs:$a2), sub_odd)>;