Lines Matching +full:asi +full:- +full:format
1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the Sparc instructions in TableGen format.
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Instruction format superclass
15 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 // True when generating 32-bit code.
24 def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
26 // True when generating 64-bit code. This also implies HasV9.
27 def Is64Bit : Predicate<"Subtarget->is64Bit()">;
29 def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">,
32 // HasV9 - This predicate is true when the target processor supports V9
33 // instructions. Note that the machine may be running in 32-bit mode.
34 def HasV9 : Predicate<"Subtarget->isV9()">,
37 // HasNoV9 - This predicate is true when the target doesn't have V9
40 def HasNoV9 : Predicate<"!Subtarget->isV9()">;
42 // HasVIS - This is true when the target processor has VIS extensions.
43 def HasVIS : Predicate<"Subtarget->isVIS()">,
45 def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
47 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
50 // HasHardQuad - This is true when the target processor supports quad floating
52 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
54 // HasLeonCASA - This is true when the target processor supports the Leon CASA
56 def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">;
58 // HasCASA - This is true when the target processor supports CASA instruction.
59 def HasCASA : Predicate<"Subtarget->hasLeonCasa() || Subtarget->isV9()">,
62 // HasPWRPSR - This is true when the target processor supports partial
64 def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">,
67 // HasUMAC_SMAC - This is true when the target processor supports the
69 def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;
71 def HasNoFdivSqrtFix : Predicate<"!Subtarget->fixAllFDIVSQRT()">;
72 def HasFMULS : Predicate<"!Subtarget->hasNoFMULS()">;
73 def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;
75 // UseDeprecatedInsts - This predicate is true when the target processor is a
79 def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;
81 //===----------------------------------------------------------------------===//
83 //===----------------------------------------------------------------------===//
85 def simm10 : PatLeaf<(imm), [{ return isInt<10>(N->getSExtValue()); }]>;
87 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
89 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
92 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
98 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
104 return CurDAG->getTargetConstant(~(unsigned)N->getZExtValue() >> 10, SDLoc(N),
109 return isShiftedUInt<22, 10>(N->getZExtValue());
112 // The N->hasOneUse() prevents the immediate from being instantiated in both
115 return N->hasOneUse() && isShiftedUInt<22, 10>(~(unsigned)N->getZExtValue());
298 // These are target-independent nodes, but have target-specific formats.
309 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
337 //===----------------------------------------------------------------------===//
339 //===----------------------------------------------------------------------===//
399 //===----------------------------------------------------------------------===//
401 //===----------------------------------------------------------------------===//
403 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
419 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
432 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
450 def rr : F3_1_asi<3, Op3Val, (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
451 !strconcat(OpcStr, "a [$addr] $asi, $rd"),
456 !strconcat(OpcStr, "a [$addr] %asi, $rd"),
460 // LoadA multiclass - As above, but also define alternate address space variant
470 // It is unlikely that general-purpose code could make use of it.
477 (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
478 "ldstuba [$addr] $asi, $rd", []>;
482 "ldstuba [$addr] %asi, $rd", []>;
484 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
503 def rr : F3_1_asi<3, Op3Val, (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd, ASITag:$asi),
504 !strconcat(OpcStr, "a $rd, [$addr] $asi"),
510 !strconcat(OpcStr, "a $rd, [$addr] %asi"),
521 //===----------------------------------------------------------------------===//
523 //===----------------------------------------------------------------------===//
557 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
624 // Section B.1 - Load Integer Instructions, p. 90
632 // Section B.2 - Load Floating-point Instructions, p. 92
682 // Section B.4 - Store Integer Instructions, p. 95
688 // Section B.5 - Store Floating-point Instructions, p. 97
741 // Section B.8 - SWAP Register with Memory Instruction
753 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi, IntRegs:$val),
754 "swapa [$addr] $asi, $rd",
759 "swapa [$addr] %asi, $rd",
764 // Section B.9 - SETHI Instruction, p. 104
771 // Section B.10 - NOP Instruction, p. 105
776 // Section B.11 - Logical Instructions, p. 106
821 // Section B.12 - Shift Instructions, p. 107
826 // Section B.13 - Add Instructions, p. 108
838 // Section B.15 - Subtract Instructions, p. 110
852 // Section B.18 - Multiply Instructions, p. 113
867 // Section B.19 - Divide Instructions, p. 115
878 // Section B.20 - SAVE and RESTORE, p. 117
882 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
883 // Section A.7 - Branch on Integer Condition Codes with Prediction (SPARC v9)
955 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
959 // floating-point conditional branch class:
963 // floating-point conditional branch with annul class:
967 // Conditional branch class on %fcc0-%fcc3 with predication:
1008 // Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 123
1011 // co-processor conditional branch class:
1015 // co-processor conditional branch with annul class:
1027 // Section B.24 - Call and Link Instruction, p. 125
1028 // This is the only Format 1 instruction
1037 let Inst{29-0} = disp;
1055 // Section B.25 - Jump and Link Instruction
1071 // Section A.3 - Synthetic Instructions, p. 85
1090 // Section B.26 - Return from Trap Instruction
1106 // Section B.27 - Trap on Integer Condition Codes Instruction
1141 // Section B.28 - Read State Register Instructions
1165 // Section B.29 - Write State Register Instructions
1203 // Section B.30 - STBAR Instruction
1208 // Section B.31 - Unimplemented Instruction
1213 // Section B.32 - Flush Instruction Memory
1220 // The no-arg FLUSH is only here for the benefit of the InstAlias
1227 // Section B.33 - Floating-point Operate (FPop) Instructions
1229 // Convert Integer to Floating-point Instructions, p. 141
1246 // Convert Floating-point to Integer Instructions, p. 142
1263 // Convert between Floating-point Formats Instructions, p. 143
1295 // Floating-point Move Instructions, p. 144
1311 // Floating-point Square Root Instructions, p.145
1333 // Floating-point Add and Subtract Instructions, p. 146
1367 // Floating-point Multiply and Divide Instructions, p. 147
1417 // Floating-point Compare Instructions, p. 148
1442 // A.13 Floating-Point Compare (SPARC v9)
1467 //===----------------------------------------------------------------------===//
1469 //===----------------------------------------------------------------------===//
1496 let Inst{29-0} = disp;
1500 //===----------------------------------------------------------------------===//
1502 //===----------------------------------------------------------------------===//
1510 let Inst{29-0} = disp;
1525 //===----------------------------------------------------------------------===//
1527 //===----------------------------------------------------------------------===//
1601 // Floating-Point Move Instructions, p. 164 of the V9 manual.
1630 // Floating-point compare instruction with %fcc0-%fcc3.
1655 // Floating point conditional move instrucitons with %fcc0-%fcc3.
1683 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
1684 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
1705 IntRegs:$swap, ASITag:$asi),
1706 "casa [$rs1] $asi, $rs2, $rd", []>;
1708 // On the other hand, CASA that takes its ASI from a register
1714 "casa [$rs1] %asi, $rs2, $rd", []>;
1717 // as inline assembler-supported instructions.
1740 // The partial write WRPSR instruction has a non-zero destination
1761 // Section A.11 - DONE and RETRY
1762 // Section A.47 - SAVED and RESTORED
1777 // Section A.42 - Prefetch Data
1786 (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi, PrefetchTag:$rd),
1787 "prefetcha [$addr] $asi, $rd", []>;
1791 "prefetcha [$addr] %asi, $rd", []>;
1796 // Section A.43 - Read Privileged Register Instructions
1813 // Section A.62 - Write Privileged Register Instructions
1823 //===----------------------------------------------------------------------===//
1824 // Non-Instruction Patterns
1825 //===----------------------------------------------------------------------===//
1838 return CurDAG->getTargetFrameIndex(N->getIndex(), N->getValueType(0));
1884 // zextload bool -> zextload byte
1888 // store 0, addr -> store %g0, addr
1899 // atomic_load addr -> load addr
1907 // atomic_store val, addr -> store val, addr
1919 // Same pattern as CASArr above, but with a different ASI.