Lines Matching refs:SP
43 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(), in SparcInstrInfo()
53 if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri || in isLoadFromStackSlot()
54 MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri || in isLoadFromStackSlot()
55 MI.getOpcode() == SP::LDQFri) { in isLoadFromStackSlot()
72 if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri || in isStoreToStackSlot()
73 MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri || in isStoreToStackSlot()
74 MI.getOpcode() == SP::STQFri) { in isStoreToStackSlot()
161 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; } in isUncondBranchOpcode()
164 return Opc == SP::BCOND || Opc == SP::BPICC || Opc == SP::BPICCA || in isI32CondBranchOpcode()
165 Opc == SP::BPICCNT || Opc == SP::BPICCANT; in isI32CondBranchOpcode()
169 return Opc == SP::BPXCC || Opc == SP::BPXCCA || Opc == SP::BPXCCNT || in isI64CondBranchOpcode()
170 Opc == SP::BPXCCANT; in isI64CondBranchOpcode()
174 return Opc == SP::BPR || Opc == SP::BPRA || Opc == SP::BPRNT || in isRegCondBranchOpcode()
175 Opc == SP::BPRANT; in isRegCondBranchOpcode()
179 return Opc == SP::FBCOND || Opc == SP::FBCONDA || Opc == SP::FBCOND_V9 || in isFCondBranchOpcode()
180 Opc == SP::FBCONDA_V9; in isFCondBranchOpcode()
189 return Opc == SP::BINDrr || Opc == SP::BINDri; in isIndirectBranchOpcode()
217 case SP::BA: in getBranchDestBlock()
218 case SP::BCOND: in getBranchDestBlock()
219 case SP::BCONDA: in getBranchDestBlock()
220 case SP::FBCOND: in getBranchDestBlock()
221 case SP::FBCONDA: in getBranchDestBlock()
222 case SP::BPICC: in getBranchDestBlock()
223 case SP::BPICCA: in getBranchDestBlock()
224 case SP::BPICCNT: in getBranchDestBlock()
225 case SP::BPICCANT: in getBranchDestBlock()
226 case SP::BPXCC: in getBranchDestBlock()
227 case SP::BPXCCA: in getBranchDestBlock()
228 case SP::BPXCCNT: in getBranchDestBlock()
229 case SP::BPXCCANT: in getBranchDestBlock()
230 case SP::BPFCC: in getBranchDestBlock()
231 case SP::BPFCCA: in getBranchDestBlock()
232 case SP::BPFCCNT: in getBranchDestBlock()
233 case SP::BPFCCANT: in getBranchDestBlock()
234 case SP::FBCOND_V9: in getBranchDestBlock()
235 case SP::FBCONDA_V9: in getBranchDestBlock()
236 case SP::BPR: in getBranchDestBlock()
237 case SP::BPRA: in getBranchDestBlock()
238 case SP::BPRNT: in getBranchDestBlock()
239 case SP::BPRANT: in getBranchDestBlock()
339 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); in insertBranch()
361 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); in insertBranch()
405 case SP::BA: in isBranchOffsetInRange()
406 case SP::BCOND: in isBranchOffsetInRange()
407 case SP::BCONDA: in isBranchOffsetInRange()
408 case SP::FBCOND: in isBranchOffsetInRange()
409 case SP::FBCONDA: in isBranchOffsetInRange()
412 case SP::BPICC: in isBranchOffsetInRange()
413 case SP::BPICCA: in isBranchOffsetInRange()
414 case SP::BPICCNT: in isBranchOffsetInRange()
415 case SP::BPICCANT: in isBranchOffsetInRange()
416 case SP::BPXCC: in isBranchOffsetInRange()
417 case SP::BPXCCA: in isBranchOffsetInRange()
418 case SP::BPXCCNT: in isBranchOffsetInRange()
419 case SP::BPXCCANT: in isBranchOffsetInRange()
420 case SP::BPFCC: in isBranchOffsetInRange()
421 case SP::BPFCCA: in isBranchOffsetInRange()
422 case SP::BPFCCNT: in isBranchOffsetInRange()
423 case SP::BPFCCANT: in isBranchOffsetInRange()
424 case SP::FBCOND_V9: in isBranchOffsetInRange()
425 case SP::FBCONDA_V9: in isBranchOffsetInRange()
428 case SP::BPR: in isBranchOffsetInRange()
429 case SP::BPRA: in isBranchOffsetInRange()
430 case SP::BPRNT: in isBranchOffsetInRange()
431 case SP::BPRANT: in isBranchOffsetInRange()
447 const unsigned DW_SubRegsIdx[] = { SP::sub_even, SP::sub_odd }; in copyPhysReg()
448 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd }; in copyPhysReg()
449 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 }; in copyPhysReg()
450 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd, in copyPhysReg()
451 SP::sub_odd64_then_sub_even, in copyPhysReg()
452 SP::sub_odd64_then_sub_odd }; in copyPhysReg()
454 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
455 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
457 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
460 movOpc = SP::ORrr; in copyPhysReg()
462 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
463 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
465 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
467 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
473 movOpc = SP::FMOVS; in copyPhysReg()
475 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
478 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
484 movOpc = SP::FMOVD; in copyPhysReg()
490 movOpc = SP::FMOVS; in copyPhysReg()
492 } else if (SP::ASRRegsRegClass.contains(DestReg) && in copyPhysReg()
493 SP::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
494 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg) in copyPhysReg()
495 .addReg(SP::G0) in copyPhysReg()
497 } else if (SP::IntRegsRegClass.contains(DestReg) && in copyPhysReg()
498 SP::ASRRegsRegClass.contains(SrcReg)) { in copyPhysReg()
499 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg) in copyPhysReg()
517 MIB.addReg(SP::G0); in copyPhysReg()
543 if (RC == &SP::I64RegsRegClass) in storeRegToStackSlot()
544 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
546 else if (RC == &SP::IntRegsRegClass) in storeRegToStackSlot()
547 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
549 else if (RC == &SP::IntPairRegClass) in storeRegToStackSlot()
550 BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
552 else if (RC == &SP::FPRegsRegClass) in storeRegToStackSlot()
553 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
555 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
556 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
558 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
561 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
582 if (RC == &SP::I64RegsRegClass) in loadRegFromStackSlot()
583 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0) in loadRegFromStackSlot()
585 else if (RC == &SP::IntRegsRegClass) in loadRegFromStackSlot()
586 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0) in loadRegFromStackSlot()
588 else if (RC == &SP::IntPairRegClass) in loadRegFromStackSlot()
589 BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0) in loadRegFromStackSlot()
591 else if (RC == &SP::FPRegsRegClass) in loadRegFromStackSlot()
592 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0) in loadRegFromStackSlot()
594 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
595 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0) in loadRegFromStackSlot()
597 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
600 BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0) in loadRegFromStackSlot()
618 Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getGlobalBaseReg()
623 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg); in getGlobalBaseReg()
652 MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri)); in expandPostRAPseudo()
654 .addReg(SP::G7) in expandPostRAPseudo()