Lines Matching full:rs1
62 // movr<cond> rs1, rs2, rd
68 // movr<cond> $rs1, $rs2, $rd
69 def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $rs2, $rd"),
70 (movrrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, condVal)>;
72 // movr<cond> $rs1, $simm10, $rd
73 def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $simm10, $rd"),
74 (movrri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, condVal)>;
76 // fmovrs<cond> $rs1, $rs2, $rd
77 def : InstAlias<!strconcat(!strconcat("fmovrs", rcond), " $rs1, $rs2, $rd"),
78 (fmovrs FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, condVal)>;
80 // fmovrd<cond> $rs1, $rs2, $rd
81 def : InstAlias<!strconcat(!strconcat("fmovrd", rcond), " $rs1, $rs2, $rd"),
82 (fmovrd DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, condVal)>;
84 // fmovrq<cond> $rs1, $rs2, $rd
86 def : InstAlias<!strconcat(!strconcat("fmovrq", rcond), " $rs1, $rs2, $rd"),
87 (fmovrq QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, condVal)>;
170 // t<cond> %icc, rs1 + rs2
171 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
172 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
180 // t<cond> %xcc, rs1 + rs2
181 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
182 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
191 // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
192 //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
193 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
200 // t<cond> %icc, rs1 + imm
201 def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),
202 (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,
208 // t<cond> %xcc, rs1 + imm
209 def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),
210 (TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,
217 // t<cond> rs1 + imm => t<cond> rs1 + imm
218 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),
219 (TRAPri IntRegs:$rs1, i32imm:$imm, condVal)>;
221 // t<cond> rs1 => t<cond> G0 + rs1
222 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1"),
223 (TRAPrr G0, IntRegs:$rs1, condVal)>;
225 // t<cond> rs1 + rs2
226 def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
227 (TRAPrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
298 // br<rcond> $rs1, $imm
299 def : InstAlias<!strconcat(!strconcat("br", rcond), " $rs1, $imm"),
300 (BPR bprtarget16:$imm, condVal, I64Regs:$rs1)>,
303 // br<rcond>,pt $rs1, $imm
304 def : InstAlias<!strconcat(!strconcat("br", rcond), ",pt $rs1, $imm"),
305 (BPR bprtarget16:$imm, condVal, I64Regs:$rs1)>,
308 // br<rcond>,pn $rs1, $imm
309 def : InstAlias<!strconcat(!strconcat("br", rcond), ",pn $rs1, $imm"),
310 (BPRNT bprtarget16:$imm, condVal, I64Regs:$rs1)>,
313 // br<rcond>,a $rs1, $imm
314 def : InstAlias<!strconcat(!strconcat("br", rcond), ",a $rs1, $imm"),
315 (BPRA bprtarget16:$imm, condVal, I64Regs:$rs1)>,
318 // br<rcond>,a,pt $rs1, $imm
319 def : InstAlias<!strconcat(!strconcat("br", rcond), ",a,pt $rs1, $imm"),
320 (BPRA bprtarget16:$imm, condVal, I64Regs:$rs1)>,
323 // br<rcond>,a,pn $rs1, $imm
324 def : InstAlias<!strconcat(!strconcat("br", rcond), ",a,pn $rs1, $imm"),
325 (BPRANT bprtarget16:$imm, condVal, I64Regs:$rs1)>,
421 // cmp rs1, reg_or_imm -> subcc rs1, reg_or_imm, %g0
422 def : InstAlias<"cmp $rs1, $rs2", (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2)>;
423 def : InstAlias<"cmp $rs1, $imm", (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm)>;
464 def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;
473 // cas [rs1], rs2, rd -> casa [rs1] #ASI_P, rs2, rd
474 def : InstAlias<"cas [$rs1], $rs2, $rd",
475 (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x80)>;
477 // casl [rs1], rs2, rd -> casa [rs1] #ASI_P_L, rs2, rd
478 def : InstAlias<"casl [$rs1], $rs2, $rd",
479 (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x88)>;
481 // casx [rs1], rs2, rd -> casxa [rs1] #ASI_P, rs2, rd
482 def : InstAlias<"casx [$rs1], $rs2, $rd",
483 (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x80)>;
485 // casxl [rs1], rs2, rd -> casxa [rs1] #ASI_P_L, rs2, rd
486 def : InstAlias<"casxl [$rs1], $rs2, $rd",
487 (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x88)>;
515 def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>;
516 def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, simm13Op:$simm13), 0>;
569 def : InstAlias<"or $simm13, $rs1, $rd", (ORri IntRegs:$rd, IntRegs:$rs1, simm13Op:$simm13)>;
572 def : InstAlias<"addx $simm13, $rs1, $rd", (ADDCri IntRegs:$rd, IntRegs:$rs1, simm13Op:$simm13)>;
594 def : InstAlias<"wrpr $rs1, $rd", (WRPRrr PRRegs:$rd, IntRegs:$rs1, G0), 0>;
638 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
639 def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
640 def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
643 def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
644 def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
646 def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
654 def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;