Lines Matching refs:SP
62 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in CC_Sparc_Assign_Split_64()
88 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in CC_Sparc_Assign_Ret_Split_64()
122 Reg = SP::I0 + Offset/8; in Analyze_CC_Sparc64_Full()
125 Reg = SP::D0 + Offset/8; in Analyze_CC_Sparc64_Full()
128 Reg = SP::F1 + Offset/4; in Analyze_CC_Sparc64_Full()
131 Reg = SP::Q0 + Offset/16; in Analyze_CC_Sparc64_Full()
165 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, in Analyze_CC_Sparc64_Half()
172 unsigned Reg = SP::I0 + Offset/8; in Analyze_CC_Sparc64_Half()
228 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7, in toCallerWindow()
230 if (Reg >= SP::I0 && Reg <= SP::I7) in toCallerWindow()
231 return Reg - SP::I0 + SP::O0; in toCallerWindow()
322 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Glue); in LowerReturn_32()
324 RetOps.push_back(DAG.getRegister(SP::I0, PtrVT)); in LowerReturn_32()
468 Register VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
483 &SP::IntRegsRegClass); in LowerFormalArguments_32()
496 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
575 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
585 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in LowerFormalArguments_32()
603 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
718 Register VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); in LowerFormalArguments_64()
740 llvm::any_of(SP::GPROutgoingArgRegClass, [TRI, &MF](MCPhysReg r) { in isAnyArgRegReserved()
744 llvm::any_of(SP::GPRIncomingArgRegClass, [TRI, &MF](MCPhysReg r) { in isAnyArgRegReserved()
934 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
954 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
988 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
997 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
1026 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
1148 .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3) in getRegisterByName()
1149 .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7) in getRegisterByName()
1150 .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3) in getRegisterByName()
1151 .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7) in getRegisterByName()
1152 .Case("l0", SP::L0).Case("l1", SP::L1).Case("l2", SP::L2).Case("l3", SP::L3) in getRegisterByName()
1153 .Case("l4", SP::L4).Case("l5", SP::L5).Case("l6", SP::L6).Case("l7", SP::L7) in getRegisterByName()
1154 .Case("g0", SP::G0).Case("g1", SP::G1).Case("g2", SP::G2).Case("g3", SP::G3) in getRegisterByName()
1155 .Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7", SP::G7) in getRegisterByName()
1193 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; in fixupVariableFloatArgs()
1200 unsigned IReg = SP::I0 + Offset/8; in fixupVariableFloatArgs()
1303 unsigned Offset = 8 * (VA.getLocReg() - SP::I0); in LowerCall_64()
1305 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT); in LowerCall_64()
1360 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT); in LowerCall_64()
1596 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering()
1598 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering()
1599 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering()
1600 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
1603 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering()
1607 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass); in SparcTargetLowering()
1881 setStackPointerRegisterToSaveRestore(SP::O6); in SparcTargetLowering()
2244 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InGlue); in LowerGlobalTLSAddress()
2256 DAG.getRegister(SP::O0, PtrVT), in LowerGlobalTLSAddress()
2263 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InGlue); in LowerGlobalTLSAddress()
2296 DAG.getRegister(SP::G7, PtrVT), Offset, in LowerGlobalTLSAddress()
2309 DAG.getRegister(SP::G7, PtrVT), Offset); in LowerGlobalTLSAddress()
2739 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT), in LowerVASTART()
2821 unsigned SPReg = SP::O6; in LowerDYNAMIC_STACKALLOC()
2822 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); in LowerDYNAMIC_STACKALLOC() local
2823 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value in LowerDYNAMIC_STACKALLOC()
2824 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain in LowerDYNAMIC_STACKALLOC()
2850 unsigned FrameReg = SP::I6; in getFRAMEADDR()
2901 Register RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR()
2933 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, in LowerF64Op()
2935 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, in LowerF64Op()
2945 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2947 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2972 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); in LowerF128Load()
2973 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); in LowerF128Load()
3011 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); in LowerF128Store()
3012 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); in LowerF128Store()
3082 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, in LowerFNEGorFABS()
3084 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, in LowerFNEGorFABS()
3101 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, in LowerFNEGorFABS()
3103 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, in LowerFNEGorFABS()
3230 return DAG.getRegister(SP::G7, PtrVT); in LowerINTRINSIC_WO_CHAIN()
3337 case SP::SELECT_CC_Int_ICC: in EmitInstrWithCustomInserter()
3338 case SP::SELECT_CC_FP_ICC: in EmitInstrWithCustomInserter()
3339 case SP::SELECT_CC_DFP_ICC: in EmitInstrWithCustomInserter()
3340 case SP::SELECT_CC_QFP_ICC: in EmitInstrWithCustomInserter()
3342 return expandSelectCC(MI, BB, SP::BPICC); in EmitInstrWithCustomInserter()
3343 return expandSelectCC(MI, BB, SP::BCOND); in EmitInstrWithCustomInserter()
3344 case SP::SELECT_CC_Int_XCC: in EmitInstrWithCustomInserter()
3345 case SP::SELECT_CC_FP_XCC: in EmitInstrWithCustomInserter()
3346 case SP::SELECT_CC_DFP_XCC: in EmitInstrWithCustomInserter()
3347 case SP::SELECT_CC_QFP_XCC: in EmitInstrWithCustomInserter()
3348 return expandSelectCC(MI, BB, SP::BPXCC); in EmitInstrWithCustomInserter()
3349 case SP::SELECT_CC_Int_FCC: in EmitInstrWithCustomInserter()
3350 case SP::SELECT_CC_FP_FCC: in EmitInstrWithCustomInserter()
3351 case SP::SELECT_CC_DFP_FCC: in EmitInstrWithCustomInserter()
3352 case SP::SELECT_CC_QFP_FCC: in EmitInstrWithCustomInserter()
3354 return expandSelectCC(MI, BB, SP::FBCOND_V9); in EmitInstrWithCustomInserter()
3355 return expandSelectCC(MI, BB, SP::FBCOND); in EmitInstrWithCustomInserter()
3404 BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI), in expandSelectCC()
3506 return std::make_pair(0U, &SP::IntPairRegClass); in getRegForInlineAsmConstraint()
3508 return std::make_pair(0U, &SP::I64RegsRegClass); in getRegForInlineAsmConstraint()
3510 return std::make_pair(0U, &SP::IntRegsRegClass); in getRegForInlineAsmConstraint()
3513 return std::make_pair(0U, &SP::FPRegsRegClass); in getRegForInlineAsmConstraint()
3515 return std::make_pair(0U, &SP::LowDFPRegsRegClass); in getRegForInlineAsmConstraint()
3517 return std::make_pair(0U, &SP::LowQFPRegsRegClass); in getRegForInlineAsmConstraint()
3522 return std::make_pair(0U, &SP::FPRegsRegClass); in getRegForInlineAsmConstraint()
3524 return std::make_pair(0U, &SP::DFPRegsRegClass); in getRegForInlineAsmConstraint()
3526 return std::make_pair(0U, &SP::QFPRegsRegClass); in getRegForInlineAsmConstraint()
3578 assert(ResultPair.second == &SP::IntRegsRegClass && in getRegForInlineAsmConstraint()
3580 return std::make_pair(ResultPair.first, &SP::I64RegsRegClass); in getRegForInlineAsmConstraint()
3621 SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), dl, SP::ASR23, MVT::i32); in ReplaceNodeResults()
3622 SDValue Hi = DAG.getCopyFromReg(Lo, dl, SP::G0, MVT::i32); in ReplaceNodeResults()
3682 assert(MI.getOpcode() == SP::SUBCCrr || MI.getOpcode() == SP::SUBCCri); in AdjustInstrPostInstrSelection()
3685 MI.getOperand(0).setReg(SP::G0); in AdjustInstrPostInstrSelection()