Lines Matching +full:1 +full:mib
78 GR->add(ElemConst, &MF, BuildVec->getOperand(1 + i).getReg()); in addConstantsToTrack()
80 BuildVec->getOperand(1 + i).setReg(ElemReg); in addConstantsToTrack()
92 MachineIRBuilder MIB(MF); in addConstantsToTrack() local
94 GR->getOrCreateSPIRVType(Const->getType(), MIB); in addConstantsToTrack()
143 ConstMI->getOperand(1).getCImm()->getZExtValue())); in foldConstantsIntoIntrinsics()
162 UseMI->getOperand(1).getReg() == Reg) in findAssignTypeInstr()
169 MachineIRBuilder MIB) { in insertBitcasts() argument
172 static_cast<const SPIRVSubtarget *>(&MIB.getMF().getSubtarget()); in insertBitcasts()
180 MIB.setInsertPt(*MI.getParent(), MI); in insertBitcasts()
183 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
189 SPIRVType *BaseTy = GR->getOrCreateSPIRVType(ElemTy, MIB); in insertBitcasts()
198 if (MachineInstr *AssignMI = findAssignTypeInstr(Def, MIB.getMRI())) in insertBitcasts()
200 MIB.getMRI()->replaceRegWith(Def, Source); in insertBitcasts()
203 MIB.buildBitcast(Def, Source); in insertBitcasts()
212 // %1 = G_GLOBAL_VALUE
213 // %2 = COPY %1
218 // %1 = G_ZEXT %2
227 MachineIRBuilder &MIB) { in propagateSPIRVType() argument
236 MIB.setInsertPt(*MI->getParent(), MI); in propagateSPIRVType()
237 Type *Ty = MI->getOperand(1).getCImm()->getType(); in propagateSPIRVType()
238 SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB); in propagateSPIRVType()
242 MIB.setInsertPt(*MI->getParent(), MI); in propagateSPIRVType()
243 const GlobalValue *Global = MI->getOperand(1).getGlobal(); in propagateSPIRVType()
247 SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB); in propagateSPIRVType()
253 if (MI->getOperand(1).isReg()) { in propagateSPIRVType()
255 MRI.getVRegDef(MI->getOperand(1).getReg())) { in propagateSPIRVType()
256 if (SPIRVType *Def = propagateSPIRVType(DefInstr, GR, MRI, MIB)) { in propagateSPIRVType()
261 SpirvTy = GR->getOrCreateSPIRVIntegerType(ExpectedBW, MIB); in propagateSPIRVType()
262 if (NumElements > 1) in propagateSPIRVType()
264 GR->getOrCreateSPIRVVectorType(SpirvTy, NumElements, MIB); in propagateSPIRVType()
272 MRI.getType(Reg).getScalarSizeInBits(), MIB); in propagateSPIRVType()
278 MachineOperand &Op = MI->getOperand(1); in propagateSPIRVType()
281 SpirvTy = propagateSPIRVType(Def, GR, MRI, MIB); in propagateSPIRVType()
288 GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF()); in propagateSPIRVType()
297 // scalar register with a bit width greater than 1 to valid sizes and cap it to
304 if (Sz == 1) in widenScalarLLTNextPow2()
306 unsigned NewSz = std::min(std::max(1u << Log2_32_Ceil(Sz), 8u), 64u); in widenScalarLLTNextPow2()
322 GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())->getOpcode() == in createNewIdReg()
372 SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB, in insertAssignInstr() argument
376 MIB.setInsertPt(*Def->getParent(), in insertAssignInstr()
379 SpirvTy = SpirvTy ? SpirvTy : GR->getOrCreateSPIRVType(Ty, MIB); in insertAssignInstr()
387 GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF()); in insertAssignInstr()
390 GR->assignSPIRVTypeToVReg(SpirvTy, NewReg, MIB.getMF()); in insertAssignInstr()
394 MIB.buildInstr(SPIRV::ASSIGN_TYPE) in insertAssignInstr()
403 void processInstr(MachineInstr &MI, MachineIRBuilder &MIB, in processInstr() argument
410 AssignTypeInst.getOperand(1).setReg(NewReg); in processInstr()
412 MIB.setInsertPt(*MI.getParent(), in processInstr()
419 MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(Op.getReg()); in processInstr()
427 MachineIRBuilder MIB, in generateAssignInstrs() argument
431 static_cast<const SPIRVSubtarget *>(&MIB.getMF().getSubtarget()); in generateAssignInstrs()
453 Register Reg = MI.getOperand(1).getReg(); in generateAssignInstrs()
454 MIB.setInsertPt(*MI.getParent(), MI.getIterator()); in generateAssignInstrs()
456 SPIRVType *BaseTy = GR->getOrCreateSPIRVType(ElementTy, MIB); in generateAssignInstrs()
465 insertAssignInstr(Reg, nullptr, AssignedPtrType, GR, MIB, in generateAssignInstrs()
469 Register Reg = MI.getOperand(1).getReg(); in generateAssignInstrs()
476 insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MF.getRegInfo()); in generateAssignInstrs()
498 ? MI.getOperand(1).getCImm()->getType() in generateAssignInstrs()
500 const ConstantInt *OpCI = MI.getOperand(1).getCImm(); in generateAssignInstrs()
515 Ty = MI.getOperand(1).getFPImm()->getType(); in generateAssignInstrs()
519 MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg()); in generateAssignInstrs()
523 ElemTy = ElemMI->getOperand(1).getCImm()->getType(); in generateAssignInstrs()
525 ElemTy = ElemMI->getOperand(1).getFPImm()->getType(); in generateAssignInstrs()
533 insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MRI); in generateAssignInstrs()
535 propagateSPIRVType(&MI, GR, MRI, MIB); in generateAssignInstrs()
563 propagateSPIRVType(&MI, GR, MRI, MIB); in generateAssignInstrs()
575 MachineIRBuilder MIB) { in processInstrsWithTypeFolding() argument
580 processInstr(MI, MIB, MRI, GR); in processInstrsWithTypeFolding()
591 Register SrcReg = MI.getOperand(1).getReg(); in processInstrsWithTypeFolding()
619 for (unsigned i = 0, Sz = ToProcess.size(); i + 1 < Sz; i += 2) { in insertInlineAsmProcess()
620 MachineInstr *I1 = ToProcess[i], *I2 = ToProcess[i + 1]; in insertInlineAsmProcess()
635 const MDNode *IAMD = I1->getOperand(1).getMetadata(); in insertInlineAsmProcess()
680 AsmDescOp += 1 + F.getNumOperandRegisters(); in insertInlineAsmProcess()
735 static void insertSpirvDecorations(MachineFunction &MF, MachineIRBuilder MIB) { in insertSpirvDecorations() argument
741 MIB.setInsertPt(*MI.getParent(), MI); in insertSpirvDecorations()
742 buildOpSpirvDecorations(MI.getOperand(1).getReg(), MIB, in insertSpirvDecorations()
754 MachineIRBuilder MIB) { in processSwitches() argument
768 if (i % 2 == 1) { in processSwitches()
775 BuildMBB->getOperand(1).isBlockAddress() && in processSwitches()
776 BuildMBB->getOperand(1).getBlockAddress()); in processSwitches()
792 Ins[i]->getOperand(1).getBlockAddress()->getBasicBlock(); in processSwitches()
802 MachineOperand::CreateCImm(Ins[i]->getOperand(1).getCImm())); in processSwitches()
805 for (unsigned i = MI.getNumOperands() - 1; i > 1; --i) in processSwitches()
826 ConstantInt::get(Type::getInt32Ty(MF.getFunction().getContext()), 1); in processSwitches()
830 BlockAddrI->getOperand(1).getBlockAddress()); in processSwitches()
859 MachineIRBuilder MIB) { in removeImplicitFallthroughs() argument
867 1); in removeImplicitFallthroughs()
868 MIB.setInsertPt(MBB, MBB.end()); in removeImplicitFallthroughs()
869 MIB.buildBr(**MBB.successors().begin()); in removeImplicitFallthroughs()
878 MachineIRBuilder MIB(MF); in runOnMachineFunction() local
885 insertBitcasts(MF, GR, MIB); in runOnMachineFunction()
886 generateAssignInstrs(MF, GR, MIB, TargetExtConstTypes); in runOnMachineFunction()
887 processSwitches(MF, GR, MIB); in runOnMachineFunction()
888 processInstrsWithTypeFolding(MF, GR, MIB); in runOnMachineFunction()
889 removeImplicitFallthroughs(MF, MIB); in runOnMachineFunction()
890 insertSpirvDecorations(MF, MIB); in runOnMachineFunction()
891 insertInlineAsm(MF, GR, ST, MIB); in runOnMachineFunction()