Lines Matching +full:eq +full:- +full:level
1 //===-- SPIRVBuiltins.td - Describe SPIRV Builtins ---------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 // Define SPIR-V external builtin/instruction sets
67 //===----------------------------------------------------------------------===//
69 // should be used to expand the builtin into either native SPIR-V instructions
77 //===----------------------------------------------------------------------===//
124 //===----------------------------------------------------------------------===//
131 //===----------------------------------------------------------------------===//
198 if !eq(set, OpenCL_std) then {
202 if !eq(set, GLSL_std_450) then {
206 if !eq(set, NonSemantic_Shader_DebugInfo_100) then {
500 //===----------------------------------------------------------------------===//
502 // SPIR-V instruction.
506 // opcode specifies the SPIR-V operation code of the generated instruction.
507 //===----------------------------------------------------------------------===//
687 //===----------------------------------------------------------------------===//
689 // SPIR-V instruction using the defined properties.
692 // opcode specifies the SPIR-V operation code of the generated instruction.
693 //===----------------------------------------------------------------------===//
697 bits<32> GroupOperation = !cond(!not(!eq(!find(name, "group_reduce"), -1)) : Reduce.Value,
698 … !not(!eq(!find(name, "group_scan_inclusive"), -1)) : InclusiveScan.Value,
699 … !not(!eq(!find(name, "group_scan_exclusive"), -1)) : ExclusiveScan.Value,
700 … !not(!eq(!find(name, "group_ballot_bit_count"), -1)) : Reduce.Value,
701 … !not(!eq(!find(name, "group_ballot_inclusive_scan"), -1)) : InclusiveScan.Value,
702 … !not(!eq(!find(name, "group_ballot_exclusive_scan"), -1)) : ExclusiveScan.Value,
703 … !not(!eq(!find(name, "group_non_uniform_reduce"), -1)) : Reduce.Value,
704 … !not(!eq(!find(name, "group_non_uniform_scan_inclusive"), -1)) : InclusiveScan.Value,
705 … !not(!eq(!find(name, "group_non_uniform_scan_exclusive"), -1)) : ExclusiveScan.Value,
706 … !not(!eq(!find(name, "group_non_uniform_reduce_logical"), -1)) : Reduce.Value,
707 … !not(!eq(!find(name, "group_non_uniform_scan_inclusive_logical"), -1)) : InclusiveScan.Value,
708 … !not(!eq(!find(name, "group_non_uniform_scan_exclusive_logical"), -1)) : ExclusiveScan.Value,
709 … !not(!eq(!find(name, "group_clustered_reduce"), -1)) : ClusteredReduce.Value,
710 … !not(!eq(!find(name, "group_clustered_reduce_logical"), -1)) : ClusteredReduce.Value,
712 bit IsElect = !eq(operation, OpGroupNonUniformElect);
713 bit IsAllOrAny = !or(!eq(operation, OpGroupAll),
714 !eq(operation, OpGroupAny),
715 !eq(operation, OpGroupNonUniformAll),
716 !eq(operation, OpGroupNonUniformAny));
717 bit IsAllEqual = !eq(operation, OpGroupNonUniformAllEqual);
718 bit IsBallot = !eq(operation, OpGroupNonUniformBallot);
719 bit IsInverseBallot = !eq(operation, OpGroupNonUniformInverseBallot);
720 bit IsBallotBitExtract = !eq(operation, OpGroupNonUniformBallotBitExtract);
721 bit IsBallotFindBit = !or(!eq(operation, OpGroupNonUniformBallotFindLSB),
722 !eq(operation, OpGroupNonUniformBallotFindMSB));
723 bit IsLogical = !or(!eq(operation, OpGroupNonUniformLogicalAnd),
724 !eq(operation, OpGroupNonUniformLogicalOr),
725 !eq(operation, OpGroupNonUniformLogicalXor),
726 !eq(operation, OpGroupLogicalAndKHR),
727 !eq(operation, OpGroupLogicalOrKHR),
728 !eq(operation, OpGroupLogicalXorKHR));
732 !eq(operation, OpGroupNonUniformShuffle),
733 !eq(operation, OpGroupNonUniformShuffleXor),
734 !eq(operation, OpGroupNonUniformShuffleUp),
735 !eq(operation, OpGroupNonUniformShuffleDown),
736 !eq(operation, OpGroupBroadcast),
737 !eq(operation, OpGroupNonUniformBroadcast),
738 !eq(operation, OpGroupNonUniformBroadcastFirst),
739 !eq(operation, OpGroupNonUniformRotateKHR));
740 bit HasBoolArg = !or(!and(IsAllOrAny, !eq(IsAllEqual, false)), IsBallot, IsLogical);
760 multiclass DemangledGroupBuiltin<string name, int level /* OnlyWork/OnlySub/... */, Op operation> {
761 assert !and(!ge(level, 0), !le(level, 2)), "group level is invalid: " # level;
763 if !or(!eq(level, OnlyWork), !eq(level, WorkOrSub)) then {
768 if !or(!eq(level, OnlySub), !eq(level, WorkOrSub)) then {
1099 //===----------------------------------------------------------------------===//
1100 // Class defining an atomic instruction on floating-point numbers.
1103 // opcode specifies the SPIR-V operation code of the generated instruction.
1104 //===----------------------------------------------------------------------===//
1110 // Table gathering all builtins for atomic instructions on floating-point numbers
1123 // corresponding builtin records for atomic instructions on floating-point numbers.
1130 // Atomic add, min and max instruction on floating-point numbers:
1135 //===----------------------------------------------------------------------===//
1137 // SPIR-V instruction using the SPV_INTEL_subgroups extension.
1140 // opcode specifies the SPIR-V operation code of the generated instruction.
1141 //===----------------------------------------------------------------------===//
1145 bit IsBlock = !or(!eq(operation, OpSubgroupBlockReadINTEL),
1146 !eq(operation, OpSubgroupBlockWriteINTEL));
1147 bit IsWrite = !eq(operation, OpSubgroupBlockWriteINTEL);
1206 //===----------------------------------------------------------------------===//
1208 // It should be translated into a SPIR-V instruction using
1212 // opcode specifies the SPIR-V operation code of the generated instruction.
1213 //===----------------------------------------------------------------------===//
1217 bit IsLogical = !or(!eq(operation, OpGroupLogicalAndKHR),
1218 !eq(operation, OpGroupLogicalOrKHR),
1219 !eq(operation, OpGroupLogicalXorKHR));
1252 //===----------------------------------------------------------------------===//
1254 // "get_sub_group_eq_mask" or "get_global_id" to SPIR-V instructions.
1259 //===----------------------------------------------------------------------===//
1306 //===----------------------------------------------------------------------===//
1313 //===----------------------------------------------------------------------===//
1350 //===----------------------------------------------------------------------===//
1356 //===----------------------------------------------------------------------===//
1360 bit IsDestinationSigned = !eq(!find(name, "convert_u"), -1);
1361 bit IsSaturated = !not(!eq(!find(name, "_sat"), -1));
1362 bit IsRounded = !not(!eq(!find(name, "_rt"), -1));
1363 bit IsBfloat16 = !or(!not(!eq(!find(name, "BF16"), -1)),
1364 !not(!eq(!find(name, "bfloat16"), -1)));
1365 FPRoundingMode RoundingMode = !cond(!not(!eq(!find(name, "_rte"), -1)) : RTE,
1366 !not(!eq(!find(name, "_rtz"), -1)) : RTZ,
1367 !not(!eq(!find(name, "_rtp"), -1)) : RTP,
1368 !not(!eq(!find(name, "_rtn"), -1)) : RTN,
1398 // those targeting floating-point types.
1399 if !eq(!find(name, "float"), -1) then {
1450 //===----------------------------------------------------------------------===//
1457 //===----------------------------------------------------------------------===//
1462 bits<32> ElementCount = !cond(!not(!eq(!find(name, "2"), -1)) : 2,
1463 !not(!eq(!find(name, "3"), -1)) : 3,
1464 !not(!eq(!find(name, "4"), -1)) : 4,
1465 !not(!eq(!find(name, "8"), -1)) : 8,
1466 !not(!eq(!find(name, "16"), -1)) : 16,
1468 bit IsRounded = !not(!eq(!find(name, "_rt"), -1));
1469 FPRoundingMode RoundingMode = !cond(!not(!eq(!find(name, "_rte"), -1)) : RTE,
1470 !not(!eq(!find(name, "_rtz"), -1)) : RTZ,
1471 !not(!eq(!find(name, "_rtp"), -1)) : RTP,
1472 !not(!eq(!find(name, "_rtn"), -1)) : RTN,
1499 if !eq(i, "") then {
1513 if !eq(i, "") then {
1522 //===----------------------------------------------------------------------===//
1523 // Class defining implementation details of SPIR-V builtin types. The info
1526 // name is the name of the given SPIR-V builtin type.
1527 // operation specifies the SPIR-V opcode the StructType should be lowered to.
1528 //===----------------------------------------------------------------------===//
1557 //===----------------------------------------------------------------------===//
1558 // Class matching an OpenCL builtin type name to an equivalent SPIR-V
1562 // spirvTypeLiteral is the literal of an equivalent SPIR-V builtin type.
1563 //===----------------------------------------------------------------------===//
1588 defvar p = !cond(!not(!eq(!find(aq, "_rw_t"), -1)) : "2",
1589 !not(!eq(!find(aq, "_wo_t"), -1)) : "1",
1596 defvar p7 = !cond(!not(!eq(!find(aq, "_rw_t"), -1)) : "2",
1597 !not(!eq(!find(aq, "_wo_t"), -1)) : "1",
1610 defvar p2 = !cond(!not(!eq(!find(a3, "_depth"), -1)) : "1", true : "0");
1611 defvar p3 = !cond(!not(!eq(!find(a1, "_array"), -1)) : "1", true : "0");
1612 defvar p4 = !cond(!not(!eq(!find(a2, "msaa"), -1)) : "1", true : "0");
1624 //===----------------------------------------------------------------------===//
1626 //===----------------------------------------------------------------------===//