332 class RISCVPassConfig : public TargetPassConfig {  class
334   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)  in RISCVPassConfig()  function in __anonf5d69f5f0111::RISCVPassConfig
380   return new RISCVPassConfig(*this, PM);  in createPassConfig()
383 FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {  in createRVVRegAllocPass()
398 bool RISCVPassConfig::addRegAssignAndRewriteFast() {  in addRegAssignAndRewriteFast()
408 bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {  in addRegAssignAndRewriteOptimized()
419 void RISCVPassConfig::addIRPasses() {  in addIRPasses()
434 bool RISCVPassConfig::addPreISel() {  in addPreISel()
451 void RISCVPassConfig::addCodeGenPrepare() {  in addCodeGenPrepare()
457 bool RISCVPassConfig::addInstSelector() {  in addInstSelector()
463 bool RISCVPassConfig::addIRTranslator() {  in addIRTranslator()
468 void RISCVPassConfig::addPreLegalizeMachineIR() {  in addPreLegalizeMachineIR()
476 bool RISCVPassConfig::addLegalizeMachineIR() {  in addLegalizeMachineIR()
481 void RISCVPassConfig::addPreRegBankSelect() {  in addPreRegBankSelect()
486 bool RISCVPassConfig::addRegBankSelect() {  in addRegBankSelect()
491 bool RISCVPassConfig::addGlobalInstructionSelect() {  in addGlobalInstructionSelect()
496 void RISCVPassConfig::addPreSched2() {  in addPreSched2()
503 void RISCVPassConfig::addPreEmitPass() {  in addPreEmitPass()
516 void RISCVPassConfig::addPreEmitPass2() {  in addPreEmitPass2()
536 void RISCVPassConfig::addMachineSSAOptimization() {  in addMachineSSAOptimization()
549 void RISCVPassConfig::addPreRegAlloc() {  in addPreRegAlloc()
567 void RISCVPassConfig::addFastRegAlloc() {  in addFastRegAlloc()
573 void RISCVPassConfig::addPostRegAlloc() {  in addPostRegAlloc()