Lines Matching +full:entry +full:- +full:latency

1 //==- RISCVSchedXiangShanNanHu.td - XS-NanHu Scheduling Defs -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 // XiangShan is a high-performance open-source RISC-V processor developed by
14 // Documentation: https://github.com/OpenXiangShan/XiangShan-doc
16 // XiangShan-NanHu is the second generation of XiangShan processor series.
17 // Overview: https://xiangshan-doc.readthedocs.io/zh-cn/latest/integration/overview/
22   let IssueWidth = 6;  // 6-way decode and dispatch
32 // The reservation stations are distributed and grouped as 32-entry or 16-entry smaller ones.
52 let Latency = 1 in {
62 let Latency = 3 in {
69 let Latency = 20, ReleaseAtCycles = [20] in {
77 let Latency = 1 in {
104 let Latency = 3 in {
130 let Latency = 5 in {
145 // XiangShan-NanHu uses FuDian FPU instead of Berkeley HardFloat.
148 let Latency = 3 in {
178 let Latency = 3 in {
183 let Latency = 5 in {
190     let Latency = 11;
193     let Latency = 18;
197     let Latency = 17;
200     let Latency = 31;
307 //===----------------------------------------------------------------------===//