Lines Matching refs:MX
256 def "_" # MInfo.MX : VPseudoBinaryNoMaskPolicy<RetClass, Op1Class, Op2Class,
266 def "_" # MInfo.MX : VPseudoTernaryNoMask_Zvk<RetClass, Op1Class, Op2Class>;
271 def "_VV_" # m.MX : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass>;
277 foreach vs2_lmul = ZvkMxSet<m.MX>.vs2_lmuls in
278 def "_VS_" # m.MX # "_" # vs2_lmul.MX : VPseudoBinaryNoMask_Zvk<m.vrclass, vs2_lmul.vrclass>;
283 defvar mx = m.MX;
291 defvar mx = m.MX;
302 defvar mx = m.MX;
313 defvar mx = m.MX;
322 defvar mx = m.MX;
331 defvar mx = m.MX;
340 defvar mx = m.MX;
349 defvar mx = m.MX;
358 defvar mx = m.MX;
367 defvar mx = m.MX;
375 defvar mx = m.MX;
384 defvar mx = m.MX;
393 defvar mx = m.MX;
402 defvar mx = m.MX;
414 defvar suffix = "_V_" # m.MX;
423 defvar mx = m.MX;
431 defvar mx = m.MX;
439 defvar mx = m.MX;
447 defvar mx = m.MX;
455 defvar mx = m.MX;
471 SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX,
474 SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX,
481 defvar mx = m.MX;
489 defvar mx = m.MX;
498 SchedBinary<"WriteVRotV", "ReadVRotV", "ReadVRotV", m.MX,
501 SchedBinary<"WriteVRotX", "ReadVRotV", "ReadVRotX", m.MX,
510 SchedUnary<"WriteVRotI", "ReadVRotV", m.MX,
577 (!cast<Instruction>(instruction_name#"_V_"#vti.LMul.MX)
597 (!cast<Instruction>("PseudoVANDN_VV_"#vti.LMul.MX)
605 (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX)
646 (!cast<Instruction>("PseudoVROR_VI_"#vti.LMul.MX)
663 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX)
670 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX)
677 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX)
697 (!cast<Instruction>(instruction_name#"_V_"#vti.LMul.MX#"_MASK")
721 (!cast<Instruction>("PseudoVANDN_VV_"#vti.LMul.MX#"_MASK")
736 (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX#"_MASK")
763 (!cast<Instruction>("PseudoVROR_VI_"#vti.LMul.MX#"_MASK")
783 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX#"_MASK")
796 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX#"_MASK")
805 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX#"_MASK")
816 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX#"_MASK")
825 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX#"_MASK")
836 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX#"_MASK")
845 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX#"_MASK")
854 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX#"_MASK")
863 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX#"_MASK")
886 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
905 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_"#vs2_lmul.MX)
921 foreach vti_vs2 = ZvkI32IntegerVectors<vti.LMul.MX>.vs2_types in
956 def : VPatBinaryNoMaskTU<intrinsic, instruction # "_VI_" # vti.LMul.MX,
964 def : VPatBinaryNoMaskTU<intrinsic, instruction # "_VV_" # vti.LMul.MX,
976 instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW,
977 instruction#"_"#kind#"_"#vti.LMul.MX),
989 !if(isSEWAware, instruction#"_VI_"#vti.LMul.MX#"_E"#vti.SEW,
990 instruction#"_VI_"#vti.LMul.MX));
1003 !if(isSEWAware, instruction#"_VI_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK",
1004 instruction#"_VI_"#vti.LMul.MX#"_MASK"));
1040 defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
1044 defm : VPatBinary<intrinsic, instruction # "_VI_" # Vti.LMul.MX,