Lines Matching +full:2 +full:b000
25 SDTCisVT<2, XLenVT>,
46 def byteselect : RISCVOp<i32>, TImmLeaf<i32, [{return isUInt<2>(Imm);}]> {
47 let ParserMatchClass = UImmAsmOperand<2>;
48 let DecoderMethod = "decodeUImmOperand<2>";
62 : RVInstR<{0b00, funct5}, 0b000, OPC_OP, (outs GPR:$rd),
65 bits<2> bs;
88 def AES64DS : ALU_rr<0b0011101, 0b000, "aes64ds">;
89 def AES64DSM : ALU_rr<0b0011111, 0b000, "aes64dsm">;
95 def AES64KS2 : ALU_rr<0b0111111, 0b000, "aes64ks2">;
106 def AES64ES : ALU_rr<0b0011001, 0b000, "aes64es">;
107 def AES64ESM : ALU_rr<0b0011011, 0b000, "aes64esm">;
118 def SHA512SIG0H : ALU_rr<0b0101110, 0b000, "sha512sig0h">;
119 def SHA512SIG0L : ALU_rr<0b0101010, 0b000, "sha512sig0l">;
120 def SHA512SIG1H : ALU_rr<0b0101111, 0b000, "sha512sig1h">;
121 def SHA512SIG1L : ALU_rr<0b0101011, 0b000, "sha512sig1l">;
122 def SHA512SUM0R : ALU_rr<0b0101000, 0b000, "sha512sum0r">;
123 def SHA512SUM1R : ALU_rr<0b0101001, 0b000, "sha512sum1r">;