Lines Matching full:gpr
72 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
82 : RVInstRBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
83 (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
93 : RVInstIShift<funct5, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
94 (ins GPR:$rs1, uimmlog2xlen:$shamt),
98 : RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
99 (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
109 (outs GPR:$rd), (ins GPR:$rs1), opcodestr, "$rd, $rs1">;
115 : RVInstIShiftW<funct7, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
116 (ins GPR:$rs1, uimm5:$shamt),
122 : RVInstR<funct7, 0b001, OPC_CUSTOM_0, (outs GPR:$rd_wb),
123 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
131 : RVInstR<funct7, 0b001, OPC_CUSTOM_0, (outs GPR:$rd_wb),
132 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
141 (outs GPR:$rd, GPR:$rs2),
142 (ins GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
155 (ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
165 : RVInstR<0b0000001, 0, OPC_CUSTOM_0, (outs), (ins GPR:$rs1),
173 : RVInstR<funct7, 0, OPC_CUSTOM_0, (outs), (ins GPR:$rs1, GPR:$rs2),
188 : RVInstRBase<!if(!eq(Ty, GPR), 0b100, 0b110), OPC_CUSTOM_0,
189 (outs Ty:$rd), (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
197 : RVInstIBase<0b100, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
198 (ins GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
211 : RVInstRBase<!if(!eq(StTy, GPR), 0b101, 0b111), OPC_CUSTOM_0,
212 (outs), (ins StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
220 : RVInstIBase<0b101, OPC_CUSTOM_0, (outs GPR:$rs1_up),
221 (ins GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
354 def TH_LRB : THLoadIndexed<GPR, 0b00000, "th.lrb">,
356 def TH_LRBU : THLoadIndexed<GPR, 0b10000, "th.lrbu">,
358 def TH_LURB : THLoadIndexed<GPR, 0b00010, "th.lurb">,
360 def TH_LURBU : THLoadIndexed<GPR, 0b10010, "th.lurbu">,
363 def TH_LRH : THLoadIndexed<GPR, 0b00100, "th.lrh">,
365 def TH_LRHU : THLoadIndexed<GPR, 0b10100, "th.lrhu">,
367 def TH_LURH : THLoadIndexed<GPR, 0b00110, "th.lurh">,
369 def TH_LURHU : THLoadIndexed<GPR, 0b10110, "th.lurhu">,
372 def TH_LRW : THLoadIndexed<GPR, 0b01000, "th.lrw">,
374 def TH_LURW : THLoadIndexed<GPR, 0b01010, "th.lurw">,
377 def TH_SRB : THStoreIndexed<GPR, 0b00000, "th.srb">,
379 def TH_SURB : THStoreIndexed<GPR, 0b00010, "th.surb">,
382 def TH_SRH : THStoreIndexed<GPR, 0b00100, "th.srh">,
384 def TH_SURH : THStoreIndexed<GPR, 0b00110, "th.surh">,
387 def TH_SRW : THStoreIndexed<GPR, 0b01000, "th.srw">,
389 def TH_SURW : THStoreIndexed<GPR, 0b01010, "th.surw">,
411 def TH_LRWU : THLoadIndexed<GPR, 0b11000, "th.lrwu">,
413 def TH_LURWU : THLoadIndexed<GPR, 0b11010, "th.lurwu">,
416 def TH_LRD : THLoadIndexed<GPR, 0b01100, "th.lrd">,
418 def TH_LURD : THLoadIndexed<GPR, 0b01110, "th.lurd">,
421 def TH_SRD : THStoreIndexed<GPR, 0b01100, "th.srd">,
423 def TH_SURD : THStoreIndexed<GPR, 0b01110, "th.surd">,
539 def : Pat<(add (XLenVT GPR:$rs1), (shl GPR:$rs2, uimm2:$uimm2)),
540 (TH_ADDSL GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
541 def : Pat<(XLenVT (riscv_shl_add GPR:$rs1, uimm2:$uimm2, GPR:$rs2)),
542 (TH_ADDSL GPR:$rs2, GPR:$rs1, uimm2:$uimm2)>;
545 def : Pat<(add_non_imm12 sh1add_op:$rs1, (XLenVT GPR:$rs2)),
546 (TH_ADDSL GPR:$rs2, sh1add_op:$rs1, 1)>;
547 def : Pat<(add_non_imm12 sh2add_op:$rs1, (XLenVT GPR:$rs2)),
548 (TH_ADDSL GPR:$rs2, sh2add_op:$rs1, 2)>;
549 def : Pat<(add_non_imm12 sh3add_op:$rs1, (XLenVT GPR:$rs2)),
550 (TH_ADDSL GPR:$rs2, sh3add_op:$rs1, 3)>;
552 def : Pat<(add (XLenVT GPR:$r), CSImm12MulBy4:$i),
553 … (TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy2XForm CSImm12MulBy4:$i))), 2)>;
554 def : Pat<(add (XLenVT GPR:$r), CSImm12MulBy8:$i),
555 … (TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), (SimmShiftRightBy3XForm CSImm12MulBy8:$i))), 3)>;
557 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 200)),
558 (SLLI (XLenVT (TH_ADDSL (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)),
559 (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)), 2)), 3)>;
566 def : Pat<(rotl (XLenVT GPR:$rs1), uimmlog2xlen:$shamt),
567 (TH_SRRI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
568 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i32), (TH_EXT GPR:$rs1, 31, 0)>;
569 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (TH_EXT GPR:$rs1, 15, 0)>;
570 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (TH_EXT GPR:$rs1, 7, 0)>;
571 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i1), (TH_EXT GPR:$rs1, 0, 0)>;
573 def : Pat<(XLenVT (ctlz (xor (XLenVT GPR:$rs1), -1))), (TH_FF0 GPR:$rs1)>;
579 def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
580 (TH_SRRIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
590 def : Pat<(and (srl (XLenVT GPR:$rs1), uimmlog2xlen:$shamt), 1),
591 (TH_TST GPR:$rs1, uimmlog2xlen:$shamt)>;
592 def : Pat<(XLenVT (seteq (and (XLenVT GPR:$rs1), SingleBitSetMask:$mask), 0)),
593 (TH_TST (XLenVT (XORI GPR:$rs1, -1)), SingleBitSetMask:$mask)>;
597 def : Pat<(select (XLenVT GPR:$cond), (XLenVT GPR:$a), (XLenVT GPR:$b)),
598 (TH_MVEQZ GPR:$a, GPR:$b, GPR:$cond)>;
599 def : Pat<(select (XLenVT GPR:$cond), (XLenVT GPR:$a), (XLenVT 0)),
600 (TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;
601 def : Pat<(select (XLenVT GPR:$cond), (XLenVT 0), (XLenVT GPR:$b)),
602 (TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
604 def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT GPR:$b)),
605 (TH_MVNEZ GPR:$a, GPR:$b, GPR:$cond)>;
606 def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT GPR:$b)),
607 (TH_MVEQZ GPR:$a, GPR:$b, GPR:$cond)>;
608 def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT 0)),
609 (TH_MVNEZ GPR:$a, (XLenVT X0), GPR:$cond)>;
610 def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT 0)),
611 (TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;
612 def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (XLenVT 0), (XLenVT GPR:$b)),
613 (TH_MVEQZ GPR:$b, (XLenVT X0), GPR:$cond)>;
614 def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (XLenVT 0), (XLenVT GPR:$b)),
615 (TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
619 def : Pat<(add GPR:$rd, (mul (XLenVT GPR:$rs1), (XLenVT GPR:$rs2))),
620 (TH_MULA GPR:$rd, GPR:$rs1, GPR:$rs2)>;
621 def : Pat<(sub GPR:$rd, (mul (XLenVT GPR:$rs1), (XLenVT GPR:$rs2))),
622 (TH_MULS GPR:$rd, GPR:$rs1, GPR:$rs2)>;
627 def : Pat<(binop_allwusers<add> GPR:$rd, (mul GPR:$rs1, GPR:$rs2)),
628 (TH_MULAW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
629 def : Pat<(binop_allwusers<sub> GPR:$rd, (mul GPR:$rs1, GPR:$rs2)),
630 (TH_MULSW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
632 def : Pat<(binop_allwusers<add> GPR:$rd, (mul
633 (sexti16 (i64 GPR:$rs1)),
634 (sexti16 (i64 GPR:$rs2)))),
635 (TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
636 def : Pat<(binop_allwusers<sub> GPR:$rd, (mul
637 (sexti16 (i64 GPR:$rs1)),
638 (sexti16 (i64 GPR:$rs2)))),
639 (TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
643 def : Pat<(i32 (add GPR:$rd, (mul (sexti16 (i32 GPR:$rs1)),
644 (sexti16 (i32 GPR:$rs2))))),
645 (TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
646 def : Pat<(i32 (sub GPR:$rd, (mul (sexti16 (i32 GPR:$rs1)),
647 (sexti16 (i32 GPR:$rs2))))),
648 (TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
694 def : Pat<(th_lwd GPR:$rs1, uimm2_3:$uimm2_3), (TH_LWD GPR:$rs1, uimm2_3:$uimm2_3, 3)>;
695 def : Pat<(th_swd GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_3:$uimm2_3),
696 (TH_SWD GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_3:$uimm2_3, 3)>;
738 def : Pat<(vt (LoadOp (AddrRegRegScale (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), uimm2:$uimm2))),
739 (Inst GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
743 def : Pat<(vt (LoadOp (AddrRegZextRegScale (i64 GPR:$rs1), (i64 GPR:$rs2), uimm2:$uimm2))),
744 (Inst GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
750 (AddrRegRegScale (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), uimm2:$uimm2)),
751 (Inst StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
757 (AddrRegZextRegScale (i64 GPR:$rs1), (i64 GPR:$rs2), uimm2:$uimm2)),
758 (Inst StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
770 defm : StIdxPat<truncstorei8, TH_SRB, GPR>;
771 defm : StIdxPat<truncstorei16, TH_SRH, GPR>;
774 defm : StIdxPat<store, TH_SRW, GPR, i32>;
797 defm : StZextIdxPat<truncstorei8, TH_SURB, GPR>;
798 defm : StZextIdxPat<truncstorei16, TH_SURH, GPR>;
799 defm : StIdxPat<truncstorei32, TH_SRW, GPR, i64>;
800 defm : StZextIdxPat<truncstorei32, TH_SURW, GPR, i64>;
801 defm : StIdxPat<store, TH_SRD, GPR, i64>;
802 defm : StZextIdxPat<store, TH_SURD, GPR>;
828 def : Pat<(st (vt GPR:$rd), GPR:$rs1, (simm5shl2 simm5:$simm5, uimm2:$uimm2)),
829 (Inst GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2)>;
859 defm : StIdxPat<truncstorei8, TH_SRB, GPR, i32>;
860 defm : StIdxPat<truncstorei16, TH_SRH, GPR, i32>;
862 defm : StZextIdxPat<truncstorei8, TH_SURB, GPR, i32>;
863 defm : StZextIdxPat<truncstorei16, TH_SURH, GPR, i32>;
864 defm : StZextIdxPat<store, TH_SURW, GPR, i32>;
868 def : Pat<(select (XLenVT GPR:$cond), (i32 GPR:$a), (i32 GPR:$b)),
869 (TH_MVEQZ GPR:$a, GPR:$b, GPR:$cond)>;
870 def : Pat<(select (XLenVT GPR:$cond), (i32 GPR:$a), (i32 0)),
871 (TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;
872 def : Pat<(select (XLenVT GPR:$cond), (i32 0), (i32 GPR:$b)),
873 (TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
875 def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 GPR:$b)),
876 (TH_MVNEZ GPR:$a, GPR:$b, GPR:$cond)>;
877 def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 GPR:$b)),
878 (TH_MVEQZ GPR:$a, GPR:$b, GPR:$cond)>;
879 def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 0)),
880 (TH_MVNEZ GPR:$a, (XLenVT X0), GPR:$cond)>;
881 def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 0)),
882 (TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;
883 def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (i32 0), (i32 GPR:$b)),
884 (TH_MVEQZ GPR:$b, (XLenVT X0), GPR:$cond)>;
885 def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (i32 0), (i32 GPR:$b)),
886 (TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
891 def : Pat<(i32 (add GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
892 (TH_MULAW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
893 def : Pat<(i32 (sub GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
894 (TH_MULSW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
896 def : Pat<(i32 (add GPR:$rd,
897 (mul (sexti16i32 (i32 GPR:$rs1)),
898 (sexti16i32 (i32 GPR:$rs2))))),
899 (TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
900 def : Pat<(i32 (sub GPR:$rd,
901 (mul (sexti16i32 (i32 GPR:$rs1)),
902 (sexti16i32 (i32 GPR:$rs2))))),
903 (TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;