Lines Matching full:rs1
68 // op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
72 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
73 opcodestr, "$vd, $rs1, $vs2$vm"> {
83 (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
84 opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
94 (ins GPR:$rs1, uimmlog2xlen:$shamt),
95 opcodestr, "$rd, $rs1, $shamt">;
99 (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
100 opcodestr, "$rd, $rs1, $msb, $lsb"> {
109 (outs GPR:$rd), (ins GPR:$rs1), opcodestr, "$rd, $rs1">;
116 (ins GPR:$rs1, uimm5:$shamt),
117 opcodestr, "$rd, $rs1, $shamt">;
123 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
124 opcodestr, "$rd, $rs1, $rs2"> {
132 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
133 opcodestr, "$rd, $rs1, $rs2"> {
142 (ins GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
143 opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
155 (ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
156 opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
165 : RVInstR<0b0000001, 0, OPC_CUSTOM_0, (outs), (ins GPR:$rs1),
166 opcodestr, "$rs1"> {
173 : RVInstR<funct7, 0, OPC_CUSTOM_0, (outs), (ins GPR:$rs1, GPR:$rs2),
174 opcodestr, "$rs1, $rs2"> {
182 let rs1 = 0;
189 (outs Ty:$rd), (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
190 opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
198 (ins GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
199 opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
205 let Constraints = "@earlyclobber $rd, $rs1_wb = $rs1";
212 (outs), (ins StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
213 opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
221 (ins GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
222 opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
228 let Constraints = "$rs1_up = $rs1";
539 def : Pat<(add (XLenVT GPR:$rs1), (shl GPR:$rs2, uimm2:$uimm2)),
540 (TH_ADDSL GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
541 def : Pat<(XLenVT (riscv_shl_add GPR:$rs1, uimm2:$uimm2, GPR:$rs2)),
542 (TH_ADDSL GPR:$rs2, GPR:$rs1, uimm2:$uimm2)>;
545 def : Pat<(add_non_imm12 sh1add_op:$rs1, (XLenVT GPR:$rs2)),
546 (TH_ADDSL GPR:$rs2, sh1add_op:$rs1, 1)>;
547 def : Pat<(add_non_imm12 sh2add_op:$rs1, (XLenVT GPR:$rs2)),
548 (TH_ADDSL GPR:$rs2, sh2add_op:$rs1, 2)>;
549 def : Pat<(add_non_imm12 sh3add_op:$rs1, (XLenVT GPR:$rs2)),
550 (TH_ADDSL GPR:$rs2, sh3add_op:$rs1, 3)>;
566 def : Pat<(rotl (XLenVT GPR:$rs1), uimmlog2xlen:$shamt),
567 (TH_SRRI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
568 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i32), (TH_EXT GPR:$rs1, 31, 0)>;
569 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (TH_EXT GPR:$rs1, 15, 0)>;
570 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (TH_EXT GPR:$rs1, 7, 0)>;
571 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i1), (TH_EXT GPR:$rs1, 0, 0)>;
573 def : Pat<(XLenVT (ctlz (xor (XLenVT GPR:$rs1), -1))), (TH_FF0 GPR:$rs1)>;
579 def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
580 (TH_SRRIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
581 def : Pat<(sra (bswap i64:$rs1), (i64 32)),
582 (TH_REVW i64:$rs1)>;
583 def : Pat<(binop_allwusers<srl> (bswap i64:$rs1), (i64 32)),
584 (TH_REVW i64:$rs1)>;
585 def : Pat<(riscv_clzw i64:$rs1),
586 (TH_FF0 (i64 (SLLI (i64 (XORI i64:$rs1, -1)), 32)))>;
590 def : Pat<(and (srl (XLenVT GPR:$rs1), uimmlog2xlen:$shamt), 1),
591 (TH_TST GPR:$rs1, uimmlog2xlen:$shamt)>;
592 def : Pat<(XLenVT (seteq (and (XLenVT GPR:$rs1), SingleBitSetMask:$mask), 0)),
593 (TH_TST (XLenVT (XORI GPR:$rs1, -1)), SingleBitSetMask:$mask)>;
619 def : Pat<(add GPR:$rd, (mul (XLenVT GPR:$rs1), (XLenVT GPR:$rs2))),
620 (TH_MULA GPR:$rd, GPR:$rs1, GPR:$rs2)>;
621 def : Pat<(sub GPR:$rd, (mul (XLenVT GPR:$rs1), (XLenVT GPR:$rs2))),
622 (TH_MULS GPR:$rd, GPR:$rs1, GPR:$rs2)>;
627 def : Pat<(binop_allwusers<add> GPR:$rd, (mul GPR:$rs1, GPR:$rs2)),
628 (TH_MULAW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
629 def : Pat<(binop_allwusers<sub> GPR:$rd, (mul GPR:$rs1, GPR:$rs2)),
630 (TH_MULSW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
633 (sexti16 (i64 GPR:$rs1)),
635 (TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
637 (sexti16 (i64 GPR:$rs1)),
639 (TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
643 def : Pat<(i32 (add GPR:$rd, (mul (sexti16 (i32 GPR:$rs1)),
645 (TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
646 def : Pat<(i32 (sub GPR:$rd, (mul (sexti16 (i32 GPR:$rs1)),
648 (TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
686 def : Pat<(th_lwud i64:$rs1, uimm2_3:$uimm2_3), (TH_LWUD i64:$rs1, uimm2_3:$uimm2_3, 3)>;
687 def : Pat<(th_ldd i64:$rs1, uimm2_4:$uimm2_4), (TH_LDD i64:$rs1, uimm2_4:$uimm2_4, 4)>;
689 def : Pat<(th_sdd i64:$rd1, i64:$rd2, i64:$rs1, uimm2_4:$uimm2_4),
690 (TH_SDD i64:$rd1, i64:$rd2, i64:$rs1, uimm2_4:$uimm2_4, 4)>;
694 def : Pat<(th_lwd GPR:$rs1, uimm2_3:$uimm2_3), (TH_LWD GPR:$rs1, uimm2_3:$uimm2_3, 3)>;
695 def : Pat<(th_swd GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_3:$uimm2_3),
696 (TH_SWD GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_3:$uimm2_3, 3)>;
738 def : Pat<(vt (LoadOp (AddrRegRegScale (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), uimm2:$uimm2))),
739 (Inst GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
743 def : Pat<(vt (LoadOp (AddrRegZextRegScale (i64 GPR:$rs1), (i64 GPR:$rs2), uimm2:$uimm2))),
744 (Inst GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
750 (AddrRegRegScale (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), uimm2:$uimm2)),
751 (Inst StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
757 (AddrRegZextRegScale (i64 GPR:$rs1), (i64 GPR:$rs2), uimm2:$uimm2)),
758 (Inst StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
828 def : Pat<(st (vt GPR:$rd), GPR:$rs1, (simm5shl2 simm5:$simm5, uimm2:$uimm2)),
829 (Inst GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2)>;
891 def : Pat<(i32 (add GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
892 (TH_MULAW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
893 def : Pat<(i32 (sub GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
894 (TH_MULSW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
897 (mul (sexti16i32 (i32 GPR:$rs1)),
899 (TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
901 (mul (sexti16i32 (i32 GPR:$rs1)),
903 (TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;