Lines Matching +full:6 +full:th
41 class THInstVdotVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
45 let Inst{6-0} = OPC_CUSTOM_0.Value;
49 class THInstVdotVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
53 let Inst{6-0} = OPC_CUSTOM_0.Value;
59 class THVdotALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr,
69 class THVdotALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr,
101 bits<6> msb;
102 bits<6> lsb;
237 multiclass THVdotVMAQA_VX<string opcodestr, bits<6> funct6> {
242 multiclass THVdotVMAQA<string opcodestr, bits<6> funct6>
253 def TH_ADDSL : THShiftALU_rri<0b001, "th.addsl">,
257 def TH_SRRI : THShift_ri<0b00010, 0b001, "th.srri">;
258 def TH_EXT : THBitfieldExtract_rii<0b010, "th.ext">;
259 def TH_EXTU : THBitfieldExtract_rii<0b011, "th.extu">;
260 def TH_FF0 : THRev_r<0b10000, 0b10, "th.ff0">;
261 def TH_FF1 : THRev_r<0b10000, 0b11, "th.ff1">;
262 def TH_REV : THRev_r<0b10000, 0b01, "th.rev">;
263 def TH_TSTNBZ : THRev_r<0b10000, 0b00, "th.tstnbz">;
267 def TH_SRRIW : THShiftW_ri<0b0001010, 0b001, "th.srriw">;
268 def TH_REVW : THRev_r<0b10010, 0b00, "th.revw">;
273 def TH_TST : RVBShift_ri<0b10001, 0b001, OPC_CUSTOM_0, "th.tst">,
277 def TH_MVEQZ : THCondMov_rr<0b0100000, "th.mveqz">;
278 def TH_MVNEZ : THCondMov_rr<0b0100001, "th.mvnez">;
282 def TH_MULA : THMulAccumulate_rr<0b0010000, "th.mula">;
283 def TH_MULS : THMulAccumulate_rr<0b0010001, "th.muls">;
287 def TH_MULAH : THMulAccumulate_rr<0b0010100, "th.mulah">;
288 def TH_MULSH : THMulAccumulate_rr<0b0010101, "th.mulsh">;
292 def TH_MULAW : THMulAccumulate_rr<0b0010010, "th.mulaw">;
293 def TH_MULSW : THMulAccumulate_rr<0b0010011, "th.mulsw">;
297 def TH_LWUD : THLoadPair<0b11110, "th.lwud">,
299 def TH_SWD : THStorePair<0b11100, "th.swd">,
302 def TH_LWD : THLoadPair<0b11100, "th.lwd">,
307 def TH_LDD : THLoadPair<0b11111, "th.ldd">,
309 def TH_SDD : THStorePair<0b11111, "th.sdd">,
315 def TH_LBIA : THLoadUpdate<0b00011, "th.lbia">,
317 def TH_LBIB : THLoadUpdate<0b00001, "th.lbib">,
319 def TH_LBUIA : THLoadUpdate<0b10011, "th.lbuia">,
321 def TH_LBUIB : THLoadUpdate<0b10001, "th.lbuib">,
324 def TH_LHIA : THLoadUpdate<0b00111, "th.lhia">,
326 def TH_LHIB : THLoadUpdate<0b00101, "th.lhib">,
328 def TH_LHUIA : THLoadUpdate<0b10111, "th.lhuia">,
330 def TH_LHUIB : THLoadUpdate<0b10101, "th.lhuib">,
333 def TH_LWIA : THLoadUpdate<0b01011, "th.lwia">,
335 def TH_LWIB : THLoadUpdate<0b01001, "th.lwib">,
338 def TH_SBIA : THStoreUpdate<0b00011, "th.sbia">,
340 def TH_SBIB : THStoreUpdate<0b00001, "th.sbib">,
343 def TH_SHIA : THStoreUpdate<0b00111, "th.shia">,
345 def TH_SHIB : THStoreUpdate<0b00101, "th.shib">,
348 def TH_SWIA : THStoreUpdate<0b01011, "th.swia">,
350 def TH_SWIB : THStoreUpdate<0b01001, "th.swib">,
354 def TH_LRB : THLoadIndexed<GPR, 0b00000, "th.lrb">,
356 def TH_LRBU : THLoadIndexed<GPR, 0b10000, "th.lrbu">,
358 def TH_LURB : THLoadIndexed<GPR, 0b00010, "th.lurb">,
360 def TH_LURBU : THLoadIndexed<GPR, 0b10010, "th.lurbu">,
363 def TH_LRH : THLoadIndexed<GPR, 0b00100, "th.lrh">,
365 def TH_LRHU : THLoadIndexed<GPR, 0b10100, "th.lrhu">,
367 def TH_LURH : THLoadIndexed<GPR, 0b00110, "th.lurh">,
369 def TH_LURHU : THLoadIndexed<GPR, 0b10110, "th.lurhu">,
372 def TH_LRW : THLoadIndexed<GPR, 0b01000, "th.lrw">,
374 def TH_LURW : THLoadIndexed<GPR, 0b01010, "th.lurw">,
377 def TH_SRB : THStoreIndexed<GPR, 0b00000, "th.srb">,
379 def TH_SURB : THStoreIndexed<GPR, 0b00010, "th.surb">,
382 def TH_SRH : THStoreIndexed<GPR, 0b00100, "th.srh">,
384 def TH_SURH : THStoreIndexed<GPR, 0b00110, "th.surh">,
387 def TH_SRW : THStoreIndexed<GPR, 0b01000, "th.srw">,
389 def TH_SURW : THStoreIndexed<GPR, 0b01010, "th.surw">,
395 def TH_LWUIA : THLoadUpdate<0b11011, "th.lwuia">,
397 def TH_LWUIB : THLoadUpdate<0b11001, "th.lwuib">,
400 def TH_LDIA : THLoadUpdate<0b01111, "th.ldia">,
402 def TH_LDIB : THLoadUpdate<0b01101, "th.ldib">,
405 def TH_SDIA : THStoreUpdate<0b01111, "th.sdia">,
407 def TH_SDIB : THStoreUpdate<0b01101, "th.sdib">,
411 def TH_LRWU : THLoadIndexed<GPR, 0b11000, "th.lrwu">,
413 def TH_LURWU : THLoadIndexed<GPR, 0b11010, "th.lurwu">,
416 def TH_LRD : THLoadIndexed<GPR, 0b01100, "th.lrd">,
418 def TH_LURD : THLoadIndexed<GPR, 0b01110, "th.lurd">,
421 def TH_SRD : THStoreIndexed<GPR, 0b01100, "th.srd">,
423 def TH_SURD : THStoreIndexed<GPR, 0b01110, "th.surd">,
431 def TH_FLRW : THLoadIndexed<FPR32, 0b01000, "th.flrw">,
433 def TH_FSRW : THStoreIndexed<FPR32, 0b01000, "th.fsrw">,
439 def TH_FLRD : THLoadIndexed<FPR64, 0b01100, "th.flrd">,
441 def TH_FSRD : THStoreIndexed<FPR64, 0b01100, "th.fsrd">,
447 def TH_FLURW : THLoadIndexed<FPR32, 0b01010, "th.flurw">,
449 def TH_FSURW : THStoreIndexed<FPR32, 0b01010, "th.fsurw">,
455 def TH_FLURD : THLoadIndexed<FPR64, 0b01110, "th.flurd">,
457 def TH_FSURD : THStoreIndexed<FPR64, 0b01110, "th.fsurd">,
462 defm THVdotVMAQA : THVdotVMAQA<"th.vmaqa", 0b100000>;
463 defm THVdotVMAQAU : THVdotVMAQA<"th.vmaqau", 0b100010>;
464 defm THVdotVMAQASU : THVdotVMAQA<"th.vmaqasu", 0b100100>;
465 defm THVdotVMAQAUS : THVdotVMAQA_VX<"th.vmaqaus",0b100110>;
565 // it can be implemented with th.srri by negating the immediate.
700 def TH_DCACHE_CSW : THCacheInst_r<0b00001, "th.dcache.csw">;
701 def TH_DCACHE_ISW : THCacheInst_r<0b00010, "th.dcache.isw">;
702 def TH_DCACHE_CISW : THCacheInst_r<0b00011, "th.dcache.cisw">;
703 def TH_DCACHE_CVAL1 : THCacheInst_r<0b00100, "th.dcache.cval1">;
704 def TH_DCACHE_CVA : THCacheInst_r<0b00101, "th.dcache.cva">;
705 def TH_DCACHE_IVA : THCacheInst_r<0b00110, "th.dcache.iva">;
706 def TH_DCACHE_CIVA : THCacheInst_r<0b00111, "th.dcache.civa">;
707 def TH_DCACHE_CPAL1 : THCacheInst_r<0b01000, "th.dcache.cpal1">;
708 def TH_DCACHE_CPA : THCacheInst_r<0b01001, "th.dcache.cpa">;
709 def TH_DCACHE_IPA : THCacheInst_r<0b01010, "th.dcache.ipa">;
710 def TH_DCACHE_CIPA : THCacheInst_r<0b01011, "th.dcache.cipa">;
711 def TH_ICACHE_IVA : THCacheInst_r<0b10000, "th.icache.iva">;
712 def TH_ICACHE_IPA : THCacheInst_r<0b11000, "th.icache.ipa">;
714 def TH_DCACHE_CALL : THCacheInst_void<0b00001, "th.dcache.call">;
715 def TH_DCACHE_IALL : THCacheInst_void<0b00010, "th.dcache.iall">;
716 def TH_DCACHE_CIALL : THCacheInst_void<0b00011, "th.dcache.ciall">;
717 def TH_ICACHE_IALL : THCacheInst_void<0b10000, "th.icache.iall">;
718 def TH_ICACHE_IALLS : THCacheInst_void<0b10001, "th.icache.ialls">;
719 def TH_L2CACHE_CALL : THCacheInst_void<0b10101, "th.l2cache.call">;
720 def TH_L2CACHE_IALL : THCacheInst_void<0b10110, "th.l2cache.iall">;
721 def TH_L2CACHE_CIALL : THCacheInst_void<0b10111, "th.l2cache.ciall">;
725 def TH_SFENCE_VMAS : THCacheInst_rr<0b0000010, "th.sfence.vmas">;
726 def TH_SYNC : THCacheInst_void<0b11000, "th.sync">;
727 def TH_SYNC_S : THCacheInst_void<0b11001, "th.sync.s">;
728 def TH_SYNC_I : THCacheInst_void<0b11010, "th.sync.i">;
729 def TH_SYNC_IS : THCacheInst_void<0b11011, "th.sync.is">;