Lines Matching full:gpr
26 : CVInstBitManipRII<funct2, funct3, (outs GPR:$rd),
27 (ins GPR:$rs1, i3type:$is3, uimm5:$is2),
31 : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
32 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
35 : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
36 (ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
54 def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
55 (ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
57 def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb),
58 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
74 (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
91 : CVInstMacMulN<funct2, funct3, (outs GPR:$rd_wb),
92 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
95 : CVInstMacMulN<funct2, funct3, (outs GPR:$rd),
96 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
153 (CV_MULSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
155 (CV_MULHHSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
159 (CV_MULUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
161 (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
166 : RVInstRBase<funct3, OPC_CUSTOM_2, (outs GPR:$rd),
167 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr,
176 : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd),
177 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
180 : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd_wb),
181 (ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
184 : RVInstIBase<funct3, OPC_CUSTOM_1, (outs GPR:$rd),
185 (ins GPR:$rs1, uimm5:$imm5), opcodestr,
194 : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins GPR:$rs1),
304 : CVInstSIMDRR<funct5, F, funct1, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
305 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
309 : CVInstSIMDRR<funct5, F, funct1, funct3, OPC_CUSTOM_3, (outs GPR:$rd_wb),
310 (ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
315 : CVInstSIMDRI<funct5, F, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
316 (ins GPR:$rs1, simm6:$imm6), opcodestr, "$rd, $rs1, $imm6">;
320 (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, simm6:$imm6),
328 (outs GPR:$rd), (ins GPR:$rs1, immtype:$imm6),
333 (outs GPR:$rd_wb),
334 (ins GPR:$rd, GPR:$rs1, uimm6:$imm6),
341 : CVInstSIMDRR<funct5, F, funct1, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
342 (ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
502 (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
505 (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
521 let MIOperandInfo = (ops GPR:$base, GPR:$offset);
525 : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, simm12:$imm12),
532 : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, GPR:$rs2),
539 : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins CVrr:$cvrr),
580 : RVInstS<funct3, OPC_CUSTOM_1, (outs GPR:$rs1_wb),
581 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
628 (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
631 (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
634 (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
643 (outs), (ins GPR:$rs2, CVrr:$cvrr),
646 (outs), (ins GPR:$rs2, CVrr:$cvrr),
649 (outs), (ins GPR:$rs2, CVrr:$cvrr),
655 : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
672 : Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, simm12:$imm12),
673 (Inst GPR:$rs2, GPR:$rs1, simm12:$imm12)>;
676 : Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, GPR:$rs3),
677 (Inst GPR:$rs2, GPR:$rs1, GPR:$rs3)>;
680 : Pat<(StoreOp (XLenVT GPR:$rs2), CVrr:$regreg),
681 (Inst GPR:$rs2, CVrr:$regreg)>;
728 def : Pat<(intr GPR:$rs1, cv_uimm10:$imm),
730 GPR:$rs1, (CV_HI5 cv_uimm10:$imm), (CV_LO5 cv_uimm10:$imm))>;
739 def : Pat<(int_riscv_cv_bitmanip_insert GPR:$rs1, GPR:$rs2, GPR:$rd),
740 (CV_INSERTR GPR:$rd, GPR:$rs1, GPR:$rs2)>;
741 def : Pat<(int_riscv_cv_bitmanip_insert GPR:$rs1, cv_uimm10:$imm, GPR:$rd),
742 (CV_INSERT GPR:$rd, GPR:$rs1, (CV_HI5 cv_uimm10:$imm),
752 def : Pat<(int_riscv_cv_bitmanip_bitrev GPR:$rs1, cv_tuimm5:$pts,
754 (CV_BITREV GPR:$rs1, cv_tuimm2:$radix, cv_tuimm5:$pts)>;
755 def : Pat<(bitreverse (XLenVT GPR:$rs)), (CV_BITREV GPR:$rs, 0, 0)>;
767 def : Pat<(intr (XLenVT GPR:$rs1), powerOf2Minus1:$upperBound),
768 (!cast<RVInst>("CV_" # NAME) GPR:$rs1,
773 def : Pat<(intr GPR:$rs1, GPR:$rs2, GPR:$rs3),
774 (!cast<RVInst>("CV_" # NAME # "R") GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
775 def : Pat<(intr GPR:$rs1, GPR:$rs2, uimm5:$imm),
776 (!cast<RVInst>("CV_" # NAME) GPR:$rs1, GPR:$rs2, uimm5:$imm)>;
788 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (CV_EXTHS GPR:$rs1)>;
789 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (CV_EXTBS GPR:$rs1)>;
790 def : Pat<(and (XLenVT GPR:$rs1), 0xffff), (CV_EXTHZ GPR:$rs1)>;
809 def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETEQ, bb:$imm12),
810 (CV_BEQIMM GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12)>;
811 def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
812 (CV_BNEIMM GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12)>;
815 def Select_GPR_Using_CC_Imm : Pseudo<(outs GPR:$dst),
816 (ins GPR:$lhs, simm5:$imm5, ixlenimm:$cc,
817 GPR:$truev, GPR:$falsev), []>;
821 : Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), simm5:$Constant, Cond,
822 (i32 GPR:$truev), GPR:$falsev),
823 (Select_GPR_Using_CC_Imm GPR:$lhs, simm5:$Constant,
824 (IntCCtoRISCVCC $cc), GPR:$truev, GPR:$falsev)>;
831 : Pat<(!cast<Intrinsic>("int_riscv_cv_mac_" # intr) GPR:$rs1, GPR:$rs2, GPR:$rd),
832 (!cast<RVInst>("CV_" # asm) GPR:$rd, GPR:$rs1, GPR:$rs2)>;
834 : Pat<(!cast<Intrinsic>("int_riscv_cv_mac_" # intr) GPR:$rs1, GPR:$rs2, GPR:$rd, cv_tuimm5:$imm5),
835 (!cast<RVInst>("CV_" # asm) GPR:$rd, GPR:$rs1, GPR:$rs2, cv_tuimm5:$imm5)>;
837 : Pat<(!cast<Intrinsic>("int_riscv_cv_mac_" # intr) GPR:$rs1, GPR:$rs2, cv_tuimm5:$imm5),
838 (!cast<RVInst>("CV_" # asm) GPR:$rs1, GPR:$rs2, cv_tuimm5:$imm5)>;