Lines Matching +full:1 +full:- +full:v0
1 //===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 def SDT_RISCVIntUnOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
31 def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
40 def SDT_RISCVVNBinOp_RM_VL : SDTypeProfile<1, 6, [SDTCisVec<0>, SDTCisInt<0>,
42 SDTCisSameNumEltsAs<0, 1>,
43 SDTCisVec<1>,
44 SDTCisOpSmallerThanOp<2, 1>,
51 def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
56 def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
64 def SDT_RISCVCopySign_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
73 SDTypeProfile<1, 3, [SDTCisVec<0>,
74 SDTCisSameAs<0, 1>,
78 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>,
79 SDTCisSameAs<0, 1>,
83 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
84 SDTCisSameAs<0, 1>,
88 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
172 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
173 SDTCisFP<1>, SDTCisVec<1>,
174 SDTCisSameSizeAs<0, 1>,
175 SDTCisSameNumEltsAs<0, 1>,
180 def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
192 def SDT_RISCVWVecFMA_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisFP<0>,
193 SDTCisVec<1>, SDTCisFP<1>,
194 SDTCisOpSmallerThanOp<1, 0>,
195 SDTCisSameNumEltsAs<0, 1>,
196 SDTCisSameAs<1, 2>,
224 def SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [
225 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>,
226 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>
228 def SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [
229 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>,
230 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>
250 def SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [
251 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>,
252 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>
254 def SDT_RISCVFP2IOp_RM_VL : SDTypeProfile<1, 4, [
255 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>,
256 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>,
260 def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [
261 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>,
262 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>
264 def SDT_RISCVI2FPOp_RM_VL : SDTypeProfile<1, 4, [
265 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>,
266 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>,
270 def SDT_RISCVSETCCOP_VL : SDTypeProfile<1, 6, [
271 SDTCVecEltisVT<0, i1>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>,
272 SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>, SDTCisSameAs<0, 4>,
275 // Float -> Int
298 // Int -> Float
332 SDTypeProfile<1, 5, [SDTCisVec<0>,
333 SDTCisSameAs<0, 1>,
340 SDTypeProfile<1, 5, [SDTCisVec<0>,
341 SDTCisSameAs<0, 1>,
350 SDTypeProfile<1, 5, [SDTCisVec<0>,
351 SDTCisSameAs<0, 1>,
360 def SDT_RISCVVMERGE_VL : SDTypeProfile<1, 5, [
361 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCVecEltisVT<1, i1>,
368 def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>,
369 SDTCisVT<1, XLenVT>]>;
373 def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
387 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,
388 SDTCisVec<1>, SDTCisInt<1>,
390 SDTCisSameNumEltsAs<1, 2>,
394 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,
395 SDTCisVec<1>, SDTCisInt<1>,
397 SDTCisSameNumEltsAs<1, 2>,
400 def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>,
401 SDTCisSameNumEltsAs<0, 1>,
402 SDTCisSameNumEltsAs<1, 2>,
412 SDTypeProfile<1, 3, [SDTCisVec<0>,
413 SDTCisSameNumEltsAs<0, 1>,
418 def SDT_RISCVVWIntBinOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>,
419 SDTCisInt<1>,
420 SDTCisSameNumEltsAs<0, 1>,
421 SDTCisOpSmallerThanOp<1, 0>,
422 SDTCisSameAs<1, 2>,
424 SDTCisSameNumEltsAs<1, 4>,
436 def SDT_RISCVVWIntTernOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>,
437 SDTCisInt<1>,
438 SDTCisSameNumEltsAs<0, 1>,
439 SDTCisOpSmallerThanOp<1, 0>,
440 SDTCisSameAs<1, 2>,
442 SDTCisSameNumEltsAs<1, 4>,
449 def SDT_RISCVVWFPBinOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisFP<0>,
450 SDTCisFP<1>,
451 SDTCisSameNumEltsAs<0, 1>,
452 SDTCisOpSmallerThanOp<1, 0>,
453 SDTCisSameAs<1, 2>,
455 SDTCisSameNumEltsAs<1, 4>,
462 def SDT_RISCVVNIntBinOp_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>,
463 SDTCisInt<1>,
464 SDTCisSameNumEltsAs<0, 1>,
465 SDTCisOpSmallerThanOp<0, 1>,
473 def SDT_RISCVVWIntBinOpW_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisInt<0>,
474 SDTCisSameAs<0, 1>,
476 SDTCisSameNumEltsAs<1, 2>,
477 SDTCisOpSmallerThanOp<2, 1>,
479 SDTCisSameNumEltsAs<1, 4>,
487 def SDT_RISCVVWFPBinOpW_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisFP<0>,
488 SDTCisSameAs<0, 1>,
490 SDTCisSameNumEltsAs<1, 2>,
491 SDTCisOpSmallerThanOp<2, 1>,
493 SDTCisSameNumEltsAs<1, 4>,
500 def SDTRVVVecReduce : SDTypeProfile<1, 6, [
501 SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>,
510 return N->hasOneUse();
517 return N->hasOneUse();
524 return N->hasOneUse();
531 return N->hasOneUse();
538 return N->hasOneUse();
545 return N->hasOneUse();
550 return N->hasOneUse();
555 return N->hasOneUse();
560 return N->hasOneUse();
565 return N->hasOneUse();
572 return N->hasOneUse();
579 return N->hasOneUse();
586 return N->hasOneUse();
593 return N->hasOneUse();
601 def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>;
602 def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [], [], 3>;
603 def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimmBits<5>", [], [], 3>;
604 def SplatPat_uimm6 : ComplexPattern<vAny, 1, "selectVSplatUimmBits<6>", [], [], 3>;
606 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 3>;
608 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 3>;
613 : ComplexPattern<vAny, 1, "selectLow8BitsVSplat", [], [], 2>;
620 def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>;
621 def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>;
622 def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>;
623 def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>;
642 (mask_type V0),
646 instruction_name#"_"#suffix#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
651 (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
669 (mask_type V0),
676 (mask_type V0),
698 (mask_type V0),
702 instruction_name#"_"#suffix#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
707 (mask_type V0),
761 (mask_type V0),
766 (mask_type V0), GPR:$vl, sew, TU_MU)>;
779 instruction_name#"_"#suffix#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_TIED",
830 (mask_type V0),
834 instruction_name#_#suffix#_#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
839 (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
858 (mask_type V0),
865 (mask_type V0),
1001 (mask_type V0),
1005 instruction_name#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
1010 (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
1027 (mask_type V0),
1031 instruction_name#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
1036 (mask_type V0),
1081 (fvti.Mask V0),
1089 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
1100 (fvti.Mask V0),
1108 (fvti.Mask V0),
1121 (vti.Mask V0),
1127 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
1137 (vti.Mask V0),
1141 vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
1150 (vti.Mask V0),
1153 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
1157 (vti.Mask V0),
1160 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
1169 (vti.Mask V0),
1172 XLenVT:$rs2, (vti.Mask V0), GPR:$vl,
1179 (vti.Mask V0),
1182 simm5:$rs2, (vti.Mask V0), GPR:$vl,
1194 (vti.Mask V0),
1197 (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
1204 (vti.Mask V0),
1207 (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
1220 (fvti.Mask V0),
1224 fvti.RegClass:$rs2, (fvti.Mask V0),
1230 (fvti.Mask V0),
1234 fvti.ScalarRegClass:$rs2, (fvti.Mask V0),
1240 (fvti.Mask V0),
1244 fvti.ScalarRegClass:$rs2, (fvti.Mask V0),
1258 (fti.Mask V0), VLOpFrag)),
1262 (fti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
1274 (fvti.Mask V0),
1278 (fvti.Mask V0), GPR:$vl, ivti.Log2SEW, TA_MA)>;
1288 (fvti.Mask V0),
1292 (fvti.Mask V0),
1307 (fvti.Mask V0), (XLenVT timm:$frm),
1311 (fvti.Mask V0), timm:$frm, GPR:$vl, ivti.Log2SEW,
1322 (ivti.Mask V0),
1326 (ivti.Mask V0),
1340 (ivti.Mask V0), (XLenVT timm:$frm),
1344 (ivti.Mask V0), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>;
1357 (fvti.Mask V0),
1361 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>;
1372 (fvti.Mask V0),
1376 (fvti.Mask V0),
1392 (fvti.Mask V0), (XLenVT timm:$frm),
1396 (fvti.Mask V0), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>;
1408 (ivti.Mask V0),
1412 (ivti.Mask V0),
1422 // direction of types around so we're converting from Wti -> Vti
1429 (fwti.Mask V0),
1433 (fwti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
1440 // direction of types around so we're converting from Wti -> Vti
1447 (fwti.Mask V0),
1451 (fwti.Mask V0),
1466 (fwti.Mask V0), (XLenVT timm:$frm),
1470 (fwti.Mask V0), timm:$frm, GPR:$vl, vti.Log2SEW, TA_MA)>;
1482 (iwti.Mask V0),
1486 (iwti.Mask V0),
1501 (iwti.Mask V0), (XLenVT timm:$frm),
1505 (iwti.Mask V0), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>;
1515 (vti.Mask V0), VLOpFrag,
1521 (vti.Mask V0), GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;
1532 (vti.Mask V0), VLOpFrag,
1538 (vti.Mask V0),
1597 VR:$rs2, (vti.Mask V0), VLOpFrag,
1601 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW,
1616 VR:$rs2, (vti.Mask V0), VLOpFrag,
1620 (wti_m1.Vector VR:$rs2), (vti.Mask V0),
1639 VR:$rs2, (vti.Mask V0), VLOpFrag,
1643 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW,
1658 VR:$rs2, (vti.Mask V0), VLOpFrag,
1662 (wti_m1.Vector VR:$rs2), (vti.Mask V0),
1788 (vti.Mask V0), VLOpFrag)),
1791 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
1834 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
1842 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>;
1843 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
1851 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>;
1852 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
1860 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
1861 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
1869 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
1883 (vti.Mask V0), VLOpFrag),
1886 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
1890 (vti.Mask V0), VLOpFrag),
1893 vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW,
1926 vti.RegClass:$rs2, (vti.Mask V0),
1930 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
1934 (vti.Mask V0),
1938 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
1948 vti.RegClass:$rs2, (vti.Mask V0),
1952 (vti.Mask V0),
1960 (vti.Mask V0),
1964 (vti.Mask V0),
1977 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
1983 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>;
1984 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
1990 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>;
1991 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
1997 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
1998 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
2004 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2013 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
2019 (vti.Mask V0),
2024 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
2030 (vti.Mask V0),
2035 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
2041 (vti.Mask V0),
2046 def : Pat<(riscv_vmerge_vl (vti.Mask V0),
2052 (vti.Mask V0),
2069 (wti.Vector wti.RegClass:$rd), (vti.Mask V0),
2073 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
2076 (wti.Vector wti.RegClass:$rd), (vti.Mask V0),
2080 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
2094 (wti.Vector wti.RegClass:$rd), (vti.Mask V0),
2098 (vti.Mask V0),
2105 (wti.Vector wti.RegClass:$rd), (vti.Mask V0),
2109 (vti.Mask V0),
2124 uimm5:$rs2, (vti.Mask V0),
2128 (vti.Mask V0), GPR:$vl, vti.Log2SEW,
2133 GPR:$rs2, (vti.Mask V0),
2137 (vti.Mask V0), GPR:$vl, vti.Log2SEW,
2148 GPR:$rs2, (vti.Mask V0), VLOpFrag)),
2151 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>;
2161 vti.Scalar:$rs2, (vti.Mask V0), VLOpFrag)),
2164 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>;
2174 vti.RegClass:$merge, (vti.Mask V0), VLOpFrag),
2177 (vti.Mask V0), vxrm, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2180 vti.RegClass:$merge, (vti.Mask V0), VLOpFrag),
2183 (vti.Mask V0), vxrm, GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2188 //===----------------------------------------------------------------------===//
2190 //===----------------------------------------------------------------------===//
2194 // 11.1. Vector Single-Width Integer Add and Subtract
2203 vti.RegClass:$merge, (vti.Mask V0), VLOpFrag),
2206 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2209 vti.RegClass:$merge, (vti.Mask V0), VLOpFrag),
2212 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2222 // shl_vl (ext_vl v, splat 1) is a special case of widening add.
2230 (vti.Mask V0), VLOpFrag)),
2232 (wti.Vector undef), 1, VLOpFrag)),
2233 wti.RegClass:$merge, (vti.Mask V0), VLOpFrag),
2236 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2239 (vti.Mask V0), VLOpFrag)),
2241 (wti.Vector undef), 1, VLOpFrag)),
2242 wti.RegClass:$merge, (vti.Mask V0), VLOpFrag),
2245 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2268 // 11.6. Vector Single-Width Bit Shift Instructions
2274 // Emit shift by 1 as an add since it might be faster.
2277 (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)),
2306 (vti.Mask V0),
2310 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
2358 // 11.10. Vector Single-Width Integer Multiply Instructions
2369 defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU", isSEWAware=1>;
2370 defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV", isSEWAware=1>;
2371 defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU", isSEWAware=1>;
2372 defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM", isSEWAware=1>;
2379 // 11.13 Vector Single-Width Integer Multiply-Add Instructions
2385 // 11.14. Vector Widening Integer Multiply-Add Instructions
2397 (vti.Mask V0), VLOpFrag),
2400 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2406 def : Pat<(vti.Vector (riscv_vmerge_vl (vti.Mask V0),
2413 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
2415 def : Pat<(vti.Vector (riscv_vmerge_vl (vti.Mask V0),
2422 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
2424 def : Pat<(vti.Vector (riscv_vmerge_vl (vti.Mask V0),
2431 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
2456 // 12. Vector Fixed-Point Arithmetic Instructions
2458 // 12.1. Vector Single-Width Saturating Add and Subtract
2464 // 12.2. Vector Single-Width Averaging Add and Subtract
2470 // 12.5. Vector Narrowing Fixed-Point Clip Instructions
2474 // 13. Vector Floating-Point Instructions
2476 // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
2477 defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fadd_vl, "PseudoVFADD", isSEWAware=1>;
2478 defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fsub_vl, "PseudoVFSUB", isSEWAware=1>;
2479 defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fsub_vl, "PseudoVFRSUB", isSEWAware=1>;
2481 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions
2483 "PseudoVFWADD", isSEWAware=1>;
2485 "PseudoVFWSUB", isSEWAware=1>;
2487 // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
2488 defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fmul_vl, "PseudoVFMUL", isSEWAware=1>;
2489 defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fdiv_vl, "PseudoVFDIV", isSEWAware=1>;
2490 defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fdiv_vl, "PseudoVFRDIV", isSEWAware=1>;
2492 // 13.5. Vector Widening Floating-Point Multiply Instructions
2493 defm : VPatBinaryFPWVL_VV_VF_RM<riscv_vfwmul_vl, "PseudoVFWMUL", isSEWAware=1>;
2495 // 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions.
2505 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
2511 // 13.11. Vector Floating-Point MIN/MAX Instructions
2512 defm : VPatBinaryFPVL_VV_VF<riscv_vfmin_vl, "PseudoVFMIN", isSEWAware=1>;
2513 defm : VPatBinaryFPVL_VV_VF<riscv_vfmax_vl, "PseudoVFMAX", isSEWAware=1>;
2515 // 13.13. Vector Floating-Point Compare Instructions
2535 // 13.8. Vector Floating-Point Square-Root Instruction
2536 def : Pat<(any_riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask V0),
2540 (vti.Mask V0),
2546 // 13.12. Vector Floating-Point Sign-Injection Instructions
2547 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask V0),
2551 vti.RegClass:$rs, (vti.Mask V0), GPR:$vl, vti.Log2SEW,
2554 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask V0),
2558 vti.RegClass:$rs, (vti.Mask V0), GPR:$vl, vti.Log2SEW,
2564 (vti.Mask V0),
2568 vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW,
2585 (vti.Mask V0),
2589 vti.ScalarRegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW,
2594 (vti.Mask V0), VLOpFrag),
2597 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
2599 // 14.14. Vector Floating-Point Classify Instruction
2601 (vti.Mask V0), VLOpFrag),
2604 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
2609 // Floating-point vselects:
2611 // 13.15. Vector Floating-Point Merge Instruction
2614 def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask V0),
2620 fvti.RegClass:$merge, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0),
2623 def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask V0),
2629 fvti.RegClass:$merge, fvti.RegClass:$rs2, GPR:$imm, (fvti.Mask V0),
2633 def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask V0),
2639 fvti.RegClass:$merge, fvti.RegClass:$rs2, 0, (fvti.Mask V0),
2646 def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask V0),
2654 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>;
2661 // 13.16. Vector Floating-Point Move Instruction
2685 // 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
2700 // 13.18. Widening Floating-Point/Integer Type-Convert Instructions
2720 (fvti.Mask V0),
2724 (fvti.Mask V0),
2734 (fvti.Mask V0),
2738 (fvti.Mask V0),
2742 // 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
2766 (fwti.Mask V0), VLOpFrag)),
2769 (fwti.Mask V0),
2779 (fwti.Mask V0), VLOpFrag)),
2782 (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>;
2792 (fwti.Mask V0), VLOpFrag)),
2795 (fwti.Mask V0),
2804 // 14.1. Vector Single-Width Integer Reduction Instructions
2821 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
2822 defm : VPatReductionVL_RM<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", is_float=1>;
2823 defm : VPatReductionVL_RM<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", is_float=1>;
2824 defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", is_float=1>;
2825 defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", is_float=1>;
2827 // 14.4. Vector Widening Floating-Point Reduction Instructions
2829 "PseudoVFWREDOSUM", is_float=1>;
2832 "PseudoVFWREDOSUM", is_float=1>;
2834 "PseudoVFWREDUSUM", is_float=1>;
2837 "PseudoVFWREDUSUM", is_float=1>;
2843 // 15.1 Vector Mask-Register Logical Instructions
2902 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask V0),
2905 VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>;
2907 // 15.3 vfirst find-first-set mask bit
2912 def : Pat<(XLenVT (riscv_vfirst_vl (mti.Mask VR:$rs2), (mti.Mask V0),
2915 VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>;
2938 (vti.Mask V0),
2942 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2945 (vti.Mask V0),
2949 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2953 (vti.Mask V0),
2957 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2964 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
2973 (vti.Mask V0),
2977 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
2981 // 16.2. Floating-Point Scalar Move Instructions
3010 (vti.Mask V0),
3014 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
3017 (vti.Mask V0),
3021 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
3026 (vti.Mask V0),
3030 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
3036 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
3046 (vti.Mask V0),
3050 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
3054 //===----------------------------------------------------------------------===//
3056 //===----------------------------------------------------------------------===//
3058 def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2,
3059 [SDTCisVec<0>, SDTCVecEltisVT<1, i1>,
3060 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>;
3062 def SDTRVVSlide : SDTypeProfile<1, 6, [
3063 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>,
3067 def SDTRVVSlide1 : SDTypeProfile<1, 5, [
3068 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisInt<0>,
3072 def SDTRVVFSlide1 : SDTypeProfile<1, 5, [
3073 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisFP<0>,
3087 def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask V0),
3090 (vti.Vector (IMPLICIT_DEF)), (vti.Mask V0), GPR:$vl, vti.Log2SEW,