Lines Matching refs:Ordered
619 bits<1> Ordered = O;
633 let Fields = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
634 let PrimaryKey = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
668 bits<1> Ordered = O;
678 let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
679 let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
703 bits<1> Ordered = O;
713 let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
714 let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
867 bit Ordered,
874 RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
889 bit Ordered,
897 RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
1328 bit Ordered>:
1333 RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
1342 bit Ordered>:
1347 RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
1695 bit Ordered> :
1700 RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
1717 bit Ordered> :
1723 RISCVVLXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
1800 bit Ordered> :
1805 RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
1818 bit Ordered> :
1823 RISCVVSXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
1895 multiclass VPseudoILoad<bit Ordered> {
1914 VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>,
1915 VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
1917 VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>,
1919 VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
1968 multiclass VPseudoIStore<bit Ordered> {
1984 VPseudoIStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
1985 VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
1987 VPseudoIStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
1988 VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
3812 multiclass VPseudoISegLoad<bit Ordered> {
3830 nf, Ordered>,
3831 VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>;
3834 nf, Ordered>,
3835 VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>;
3878 multiclass VPseudoISegStore<bit Ordered> {
3896 nf, Ordered>,
3897 VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>;
3900 nf, Ordered>,
3901 VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>;
6171 defm PseudoVLUX : VPseudoILoad<Ordered=false>;
6172 defm PseudoVLOX : VPseudoILoad<Ordered=true>;
6173 defm PseudoVSOX : VPseudoIStore<Ordered=true>;
6174 defm PseudoVSUX : VPseudoIStore<Ordered=false>;
6189 defm PseudoVLOXSEG : VPseudoISegLoad<Ordered=true>;
6190 defm PseudoVLUXSEG : VPseudoISegLoad<Ordered=false>;
6193 defm PseudoVSOXSEG : VPseudoISegStore<Ordered=true>;
6194 defm PseudoVSUXSEG : VPseudoISegStore<Ordered=false>;