Lines Matching refs:Masked
23 /// Masked vs Unmasked - Many instructions which allow a mask disallow register
580 bits<1> Masked = M;
596 let Fields = ["Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
597 let PrimaryKey = ["Masked", "Strided", "FF", "Log2SEW", "LMUL"];
602 bits<1> Masked = M;
612 let Fields = ["Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"];
613 let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];
618 bits<1> Masked = M;
633 let Fields = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
634 let PrimaryKey = ["Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
649 bits<1> Masked = M;
660 let Fields = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
661 let PrimaryKey = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL"];
667 bits<1> Masked = M;
678 let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
679 let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
685 bits<1> Masked = M;
695 let Fields = ["NF", "Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"];
696 let PrimaryKey = ["NF", "Masked", "Strided", "Log2SEW", "LMUL"];
702 bits<1> Masked = M;
713 let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
714 let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
767 RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
784 RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
801 RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
818 RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
835 RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
852 RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
874 RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
897 RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
914 RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
928 RISCVVSE</*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
942 RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
956 RISCVVSE</*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
1333 RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
1347 RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
1591 RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
1608 RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
1626 RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
1643 RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
1661 RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
1679 RISCVVLSEG<NF, /*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
1700 RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
1723 RISCVVLXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
1742 RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
1757 RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
1772 RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
1787 RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
1805 RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
1823 RISCVVSXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {