Lines Matching full:vreg
140 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
141 VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {
143 VReg vrclass = regclass;
144 VReg wvrclass = wregclass;
145 VReg f8vrclass = f8regclass;
146 VReg f4vrclass = f4regclass;
147 VReg f2vrclass = f2regclass;
245 VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
261 VReg RegClass = M.vrclass;
726 class GetVRegNoV0<VReg VRegClass> {
727 VReg R = !cond(!eq(VRegClass, VR) : VRNoV0,
761 class VPseudoUSLoadNoMask<VReg RetClass,
777 class VPseudoUSLoadMask<VReg RetClass,
795 class VPseudoUSLoadFFNoMask<VReg RetClass,
811 class VPseudoUSLoadFFMask<VReg RetClass,
829 class VPseudoSLoadNoMask<VReg RetClass,
845 class VPseudoSLoadMask<VReg RetClass,
863 class VPseudoILoadNoMask<VReg RetClass,
864 VReg IdxClass,
885 class VPseudoILoadMask<VReg RetClass,
886 VReg IdxClass,
909 class VPseudoUSStoreNoMask<VReg StClass,
922 class VPseudoUSStoreMask<VReg StClass,
936 class VPseudoSStoreNoMask<VReg StClass,
950 class VPseudoSStoreMask<VReg StClass,
964 class VPseudoNullaryNoMask<VReg RegClass> :
978 class VPseudoNullaryMask<VReg RegClass> :
1064 class VPseudoUnaryMask<VReg RetClass,
1065 VReg OpClass,
1083 class VPseudoUnaryMaskRoundingMode<VReg RetClass,
1084 VReg OpClass,
1105 class VPseudoUnaryMask_NoExcept<VReg RetClass,
1106 VReg OpClass,
1122 class VPseudoUnaryNoMask_FRM<VReg RetClass,
1123 VReg OpClass,
1141 class VPseudoUnaryMask_FRM<VReg RetClass,
1142 VReg OpClass,
1185 class VPseudoUnaryAnyMask<VReg RetClass,
1186 VReg Op1Class> :
1199 class VPseudoBinaryNoMask<VReg RetClass,
1200 VReg Op1Class,
1216 class VPseudoBinaryNoMaskPolicy<VReg RetClass,
1217 VReg Op1Class,
1235 class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
1236 VReg Op1Class,
1256 class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
1283 class VPseudoTiedBinaryNoMask<VReg RetClass,
1303 class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
1327 class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
1341 class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
1355 class VPseudoBinaryMaskPolicy<VReg RetClass,
1376 class VPseudoTernaryMaskPolicy<VReg RetClass,
1393 class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
1415 class VPseudoBinaryMOutMask<VReg RetClass,
1438 class VPseudoTiedBinaryMask<VReg RetClass,
1459 class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
1484 class VPseudoBinaryCarry<VReg RetClass,
1485 VReg Op1Class,
1508 class VPseudoTiedBinaryCarryIn<VReg RetClass,
1509 VReg Op1Class,
1528 class VPseudoTernaryNoMask<VReg RetClass,
1544 class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
1563 class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
1584 class VPseudoUSSegLoadNoMask<VReg RetClass,
1601 class VPseudoUSSegLoadMask<VReg RetClass,
1619 class VPseudoUSSegLoadFFNoMask<VReg RetClass,
1636 class VPseudoUSSegLoadFFMask<VReg RetClass,
1654 class VPseudoSSegLoadNoMask<VReg RetClass,
1671 class VPseudoSSegLoadMask<VReg RetClass,
1690 class VPseudoISegLoadNoMask<VReg RetClass,
1691 VReg IdxClass,
1712 class VPseudoISegLoadMask<VReg RetClass,
1713 VReg IdxClass,
1736 class VPseudoUSSegStoreNoMask<VReg ValClass,
1750 class VPseudoUSSegStoreMask<VReg ValClass,
1765 class VPseudoSSegStoreNoMask<VReg ValClass,
1780 class VPseudoSSegStoreMask<VReg ValClass,
1795 class VPseudoISegStoreNoMask<VReg ValClass,
1796 VReg IdxClass,
1813 class VPseudoISegStoreMask<VReg ValClass,
1814 VReg IdxClass,
1835 defvar vreg = lmul.vrclass;
1838 VPseudoUSLoadNoMask<vreg, eew>,
1841 VPseudoUSLoadMask<vreg, eew>,
1853 defvar vreg = lmul.vrclass;
1856 VPseudoUSLoadFFNoMask<vreg, eew>,
1859 VPseudoUSLoadFFMask<vreg, eew>,
1882 defvar vreg = lmul.vrclass;
1884 def "E" # eew # "_V_" # LInfo : VPseudoSLoadNoMask<vreg, eew>,
1887 VPseudoSLoadMask<vreg, eew>,
1907 defvar Vreg = dataEMUL.vrclass;
1914 VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>,
1917 VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>,
1931 defvar vreg = lmul.vrclass;
1933 def "E" # eew # "_V_" # LInfo : VPseudoUSStoreNoMask<vreg, eew>,
1935 def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg, eew>,
1957 defvar vreg = lmul.vrclass;
1959 def "E" # eew # "_V_" # LInfo : VPseudoSStoreNoMask<vreg, eew>,
1961 def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSStoreMask<vreg, eew>,
1980 defvar Vreg = dataEMUL.vrclass;
1984 VPseudoIStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
1987 VPseudoIStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
2091 multiclass VPseudoBinary<VReg RetClass,
2092 VReg Op1Class,
2109 multiclass VPseudoBinaryRoundingMode<VReg RetClass,
2110 VReg Op1Class,
2134 multiclass VPseudoBinaryM<VReg RetClass,
2135 VReg Op1Class,
2151 multiclass VPseudoBinaryEmul<VReg RetClass,
2152 VReg Op1Class,
2168 multiclass VPseudoTiedBinary<VReg RetClass,
2182 multiclass VPseudoTiedBinaryRoundingMode<VReg RetClass,
3156 multiclass VPseudoTernaryWithTailPolicy<VReg RetClass,
3169 multiclass VPseudoTernaryWithTailPolicyRoundingMode<VReg RetClass,
3186 multiclass VPseudoTernaryWithPolicy<VReg RetClass,
3201 multiclass VPseudoTernaryWithPolicyRoundingMode<VReg RetClass,
3274 multiclass VPseudoVSLDVWithPolicy<VReg RetClass,
3533 multiclass VPseudoConversion<VReg RetClass,
3534 VReg Op1Class,
3548 multiclass VPseudoConversionRoundingMode<VReg RetClass,
3549 VReg Op1Class,
3565 multiclass VPseudoConversionRM<VReg RetClass,
3566 VReg Op1Class,
3581 multiclass VPseudoConversionNoExcept<VReg RetClass,
3582 VReg Op1Class,
3767 defvar vreg = SegRegClass<lmul, nf>.RC;
3769 VPseudoUSSegLoadNoMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
3771 VPseudoUSSegLoadMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
3784 defvar vreg = SegRegClass<lmul, nf>.RC;
3786 VPseudoUSSegLoadFFNoMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
3788 VPseudoUSSegLoadFFMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
3801 defvar vreg = SegRegClass<lmul, nf>.RC;
3802 def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask<vreg, eew, nf>,
3804 def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegLoadMask<vreg, eew, nf>,
3827 defvar Vreg = SegRegClass<dataEMUL, nf>.RC;
3829 VPseudoISegLoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
3833 VPseudoISegLoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
3850 defvar vreg = SegRegClass<lmul, nf>.RC;
3851 def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew, nf>,
3853 def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegStoreMask<vreg, eew, nf>,
3867 defvar vreg = SegRegClass<lmul, nf>.RC;
3868 def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask<vreg, eew, nf>,
3870 def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegStoreMask<vreg, eew, nf>,
3893 defvar Vreg = SegRegClass<dataEMUL, nf>.RC;
3895 VPseudoISegStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
3899 VPseudoISegStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
3921 VReg result_reg_class,
3922 VReg op2_reg_class,
3943 VReg result_reg_class,
3944 VReg op2_reg_class,
3967 VReg result_reg_class,
3968 VReg op2_reg_class,
3991 VReg result_reg_class,
3992 VReg op2_reg_class,
4015 VReg result_reg_class,
4016 VReg op2_reg_class,
4042 VReg result_reg_class,
4043 VReg op2_reg_class,
4091 VReg result_reg_class,
4092 VReg op1_reg_class> :
4110 VReg op1_reg_class,
4127 VReg result_reg_class,
4128 VReg op1_reg_class,
4147 VReg result_reg_class,
4148 VReg op1_reg_class,
4171 VReg op1_reg_class,
4189 VReg result_reg_class,
4190 VReg op1_reg_class,
4211 VReg result_reg_class,
4212 VReg op1_reg_class,
4233 VReg result_reg_class,
4234 VReg op1_reg_class,
4259 VReg result_reg_class,
4260 VReg op1_reg_class,
4279 VReg result_reg_class,
4296 VReg result_reg_class,
4315 VReg result_reg_class,
4332 VReg result_reg_class,
4352 VReg result_reg_class,
4371 VReg result_reg_class,
4395 VReg result_reg_class,
4417 VReg result_reg_class,
4441 VReg result_reg_class,
4463 VReg result_reg_class,
4491 VReg result_reg_class,
4516 VReg result_reg_class,
4546 VReg result_reg_class,
4571 VReg result_reg_class,
4710 VReg result_reg_class,
4711 VReg op1_reg_class,
4727 VReg result_reg_class,
4728 VReg op1_reg_class,
4744 VReg result_reg_class,
4745 VReg op1_reg_class,
4761 VReg result_reg_class,
4762 VReg op1_reg_class,
4780 VReg result_reg_class,
4781 VReg op1_reg_class,
4805 VReg op1_reg_class,
4826 VReg op1_reg_class,
4846 VReg result_reg_class,
4847 VReg op1_reg_class,
4865 VReg result_reg_class,
4866 VReg op1_reg_class,
4884 VReg result_reg_class,
4885 VReg op1_reg_class,
5506 VReg result_reg_class,
5526 VReg result_reg_class,
5549 VReg result_reg_class,
5569 VReg result_reg_class,
6102 defvar vreg = SegRegClass<lmul, nf>.RC;
6106 Pseudo<(outs), (ins vreg:$rs1, GPR:$rs2), []>;
6111 Pseudo<(outs vreg:$rs1), (ins GPR:$rs2), []>;