Lines Matching +full:mx +full:- +full:specific
1 //===-- RISCVInstrInfoVPseudos.td - RISC-V 'V' Pseudos -----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 /// the compiler - e.g. register allocation - depend on fields in this
18 /// specific instruction, but the common dimensions are:
20 /// LMUL/EMUL - Most instructions can write to differently sized register groups
23 /// Masked vs Unmasked - Many instructions which allow a mask disallow register
27 /// Policy - For each of mask and tail policy, there are three options:
28 /// * "Undisturbed" - As defined in the specification, required to preserve the
30 /// * "Agnostic" - As defined in the specification, required to either preserve
31 /// the exact bit pattern of inactive lanes, or produce the bit pattern -1 for
34 /// option of producing a result as-if VL had been VLMAX.
35 /// * "Undefined" - The bit pattern of the inactive lanes is unspecified, and
40 /// SEW - Some instructions have semantics which depend on SEW. This is
48 /// legacy - see policy discussion below), we define a family of pseudo
54 /// * _MASK - Can represent all three policy states for both tail and mask. If
57 /// (If policy operand is not present - there are a couple, though we're
58 /// rapidly removing them - a non-undefined policy defaults to "tail
65 /// * Unsuffixed w/o passthrough or policy operand -- Does not have a
71 //===----------------------------------------------------------------------===//
80 // immediate, or -1. -1 means VLMAX. This allows us to pick between VSETIVLI and
89 //--------------------------------------------------------------
95 return CurDAG->getTargetConstant(N->getSExtValue() - 1, SDLoc(N),
96 N->getValueType(0));
103 //===----------------------------------------------------------------------===//
105 //===----------------------------------------------------------------------===//
141 VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {
148 string MX = mx;
174 // For widening floating-point Reduction as it doesn't contain MF8. It can
237 def VLMax : OutPatFrag<(ops), (XLenVT -1)>;
245 VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
246 !eq(m.value, V_MF4.value): V_M1.MX,
247 !eq(m.value, V_MF2.value): V_M1.MX,
248 true: m.MX));
251 //===----------------------------------------------------------------------===//
253 //===----------------------------------------------------------------------===//
526 // SEW = 0 is used to denote that the Pseudo is not SEW specific (or unknown).
718 //===----------------------------------------------------------------------===//
720 //===----------------------------------------------------------------------===//
1004 // Just fill a corresponding real v-inst to pass tablegen check.
1834 defvar LInfo = lmul.MX;
1852 defvar LInfo = lmul.MX;
1869 defvar mx = mti.LMul.MX;
1870 defvar WriteVLDM_MX = !cast<SchedWrite>("WriteVLDM_" # mx);
1881 defvar LInfo = lmul.MX;
1904 defvar DataLInfo = dataEMUL.MX;
1930 defvar LInfo = lmul.MX;
1944 defvar mx = mti.LMul.MX;
1945 defvar WriteVSTM_MX = !cast<SchedWrite>("WriteVSTM_" # mx);
1956 defvar LInfo = lmul.MX;
1977 defvar DataLInfo = dataEMUL.MX;
1998 defvar mx = mti.LMul.MX;
2001 SchedBinary<"WriteVMPopV", "ReadVMPopV", "ReadVMPopV", mx>;
2003 SchedBinary<"WriteVMPopV", "ReadVMPopV", "ReadVMPopV", mx>;
2010 defvar mx = mti.LMul.MX;
2013 SchedBinary<"WriteVMFFSV", "ReadVMFFSV", "ReadVMFFSV", mx>;
2015 SchedBinary<"WriteVMFFSV", "ReadVMFFSV", "ReadVMFFSV", mx>;
2023 defvar mx = mti.LMul.MX;
2026 SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx,
2030 SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx,
2038 defvar mx = m.MX;
2040 def "_V_" # mx : VPseudoNullaryNoMask<m.vrclass>,
2041 SchedNullary<"WriteVIdxV", mx, forceMergeOpRead=true>;
2042 def "_V_" # mx # "_MASK" : VPseudoNullaryMask<m.vrclass>,
2044 SchedNullary<"WriteVIdxV", mx,
2054 SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mti.LMul.MX>;
2062 defvar mx = m.MX;
2064 def "_" # mx : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
2065 SchedUnary<"WriteVIotaV", "ReadVIotaV", mx,
2067 def "_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
2069 SchedUnary<"WriteVIotaV", "ReadVIotaV", mx,
2077 defvar mx = m.MX;
2078 defvar sews = SchedSEWSet<mx>.val;
2081 defvar suffix = "_" # m.MX # "_E" # e;
2086 mx, e>;
2100 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
2119 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
2142 def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
2145 def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
2159 defvar suffix = !if(sew, "_" # lmul.MX # "_E" # sew, "_" # lmul.MX);
2160 def suffix # "_" # emul.MX : VPseudoBinaryNoMaskPolicy<RetClass, Op1Class, Op2Class,
2162 def suffix # "_" # emul.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
2174 def "_" # MInfo.MX # "_TIED": VPseudoTiedBinaryNoMask<RetClass, Op2Class,
2176 def "_" # MInfo.MX # "_MASK_TIED" : VPseudoTiedBinaryMask<RetClass, Op2Class,
2188 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
2216 defvar mx = m.MX;
2224 defvar sews = SchedSEWSet<mx>.val;
2230 "ReadVRGatherEI16VV_index", mx, e, forceMergeOpRead=true>;
2249 m.MX, forceMergeOpRead=true>;
2269 SchedBinary<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF", m.MX,
2285 defvar mx = m.MX;
2287 def "_MM_" # mx : VPseudoBinaryNoMask<VR, VR, VR, "">,
2288 SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mx>;
2295 // in the lowest-numbered part of the source register group is legal.
2298 // at least 1, and the overlap is in the highest-numbered part of the
2363 // lowest-numbered part of the source register group."
2411 def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
2420 def "_VVM" # "_" # m.MX:
2427 def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
2435 def "_VXM" # "_" # m.MX:
2443 defvar mx = m.MX;
2444 def "_V" # f.FX # "M_" # mx
2447 SchedBinary<"WriteVFMergeV", "ReadVFMergeV", "ReadVFMergeF", mx,
2455 def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
2463 def "_VIM" # "_" # m.MX:
2471 defvar mx = m.MX;
2473 def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
2474 SchedUnary<"WriteVIMovV", "ReadVIMovV", mx,
2476 def "_X_" # mx : VPseudoUnaryNoMask<m.vrclass, GPR>,
2477 SchedUnary<"WriteVIMovX", "ReadVIMovX", mx,
2479 def "_I_" # mx : VPseudoUnaryNoMask<m.vrclass, simm5>,
2480 SchedNullary<"WriteVIMovI", mx,
2490 defvar mx = m.MX;
2492 def "_" # f.FX # "_" # mx :
2494 SchedUnary<"WriteVFMovV", "ReadVFMovF", mx, forceMergeOpRead=true>;
2502 defvar mx = m.MX;
2504 def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
2505 SchedUnary<"WriteVFClassV", "ReadVFClassV", mx,
2507 def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
2509 SchedUnary<"WriteVFClassV", "ReadVFClassV", mx,
2517 defvar mx = m.MX;
2518 defvar sews = SchedSEWSet<m.MX, isF=1>.val;
2522 defvar suffix = "_" # mx # "_E" # e;
2525 SchedUnary<"WriteVFSqrtV", "ReadVFSqrtV", mx, e,
2530 SchedUnary<"WriteVFSqrtV", "ReadVFSqrtV", mx, e,
2539 defvar mx = m.MX;
2540 foreach e = SchedSEWSet<mx, isF=1>.val in {
2542 def "_V_" # mx # "_E" # e
2544 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forceMergeOpRead=true>;
2545 def "_V_" # mx # "_E" # e # "_MASK"
2548 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forceMergeOpRead=true>;
2556 defvar mx = m.MX;
2557 foreach e = SchedSEWSet<mx, isF=1>.val in {
2559 def "_V_" # mx # "_E" # e
2561 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forceMergeOpRead=true>;
2562 def "_V_" # mx # "_E" # e # "_MASK"
2565 SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, e, forceMergeOpRead=true>;
2574 defvar mx = m.MX;
2575 defvar CurrTypeConstraints = !if(!or(!eq(mx, "MF4"), !eq(mx, "MF2"), !eq(mx, "M1")), 1, 3);
2577 def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints, CurrTypeConstraints>,
2578 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
2579 def "_" # mx # "_MASK" :
2582 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
2590 defvar mx = m.MX;
2591 defvar CurrTypeConstraints = !if(!or(!eq(mx, "MF2"), !eq(mx, "M1"), !eq(mx, "M2")), 1, 3);
2593 def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints, CurrTypeConstraints>,
2594 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
2595 def "_" # mx # "_MASK" :
2598 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
2606 defvar mx = m.MX;
2607 defvar CurrTypeConstraints = !if(!or(!eq(mx, "M1"), !eq(mx, "M2"), !eq(mx, "M4")), 1, 3);
2609 def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints, CurrTypeConstraints>,
2610 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
2611 def "_" # mx # "_MASK" :
2614 SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
2627 // lowest-numbered part of the source register group".
2629 // is in the lowest-numbered part.
2657 defvar mx = m.MX;
2660 "ReadVRGatherVX_index", mx, forceMergeOpRead=true>;
2662 SchedUnary<"WriteVRGatherVI", "ReadVRGatherVI_data", mx,
2665 defvar sews = SchedSEWSet<mx>.val;
2669 "ReadVRGatherVV_index", mx, e, forceMergeOpRead=true>;
2676 defvar mx = m.MX;
2678 SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx,
2681 SchedBinary<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx,
2684 SchedUnary<"WriteVSALUI", "ReadVSALUV", mx, forceMergeOpRead=true>;
2691 defvar mx = m.MX;
2693 SchedBinary<"WriteVShiftV", "ReadVShiftV", "ReadVShiftV", mx,
2696 SchedBinary<"WriteVShiftX", "ReadVShiftV", "ReadVShiftX", mx,
2699 SchedUnary<"WriteVShiftI", "ReadVShiftV", mx, forceMergeOpRead=true>;
2705 defvar mx = m.MX;
2707 SchedBinary<"WriteVSShiftV", "ReadVSShiftV", "ReadVSShiftV", mx,
2710 SchedBinary<"WriteVSShiftX", "ReadVSShiftV", "ReadVSShiftX", mx,
2713 SchedUnary<"WriteVSShiftI", "ReadVSShiftV", mx, forceMergeOpRead=true>;
2719 defvar mx = m.MX;
2721 SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
2724 SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,
2727 SchedUnary<"WriteVIALUI", "ReadVIALUV", mx, forceMergeOpRead=true>;
2733 defvar mx = m.MX;
2735 SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUV", mx,
2738 SchedBinary<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx,
2745 defvar mx = m.MX;
2747 SchedBinary<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV", mx,
2750 SchedBinary<"WriteVSMulX", "ReadVSMulV", "ReadVSMulX", mx,
2757 defvar mx = m.MX;
2759 SchedBinary<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV", mx,
2762 SchedBinary<"WriteVAALUX", "ReadVAALUV", "ReadVAALUX", mx,
2769 defvar mx = m.MX;
2771 SchedBinary<"WriteVIMinMaxV", "ReadVIMinMaxV", "ReadVIMinMaxV", mx>;
2773 SchedBinary<"WriteVIMinMaxX", "ReadVIMinMaxV", "ReadVIMinMaxX", mx>;
2779 defvar mx = m.MX;
2781 SchedBinary<"WriteVIMulV", "ReadVIMulV", "ReadVIMulV", mx>;
2783 SchedBinary<"WriteVIMulX", "ReadVIMulV", "ReadVIMulX", mx>;
2789 defvar mx = m.MX;
2790 defvar sews = SchedSEWSet<mx>.val;
2793 SchedBinary<"WriteVIDivV", "ReadVIDivV", "ReadVIDivV", mx, e>;
2795 SchedBinary<"WriteVIDivX", "ReadVIDivV", "ReadVIDivX", mx, e>;
2802 foreach e = SchedSEWSet<m.MX, isF=1>.val in
2804 SchedBinary<"WriteVFMulV", "ReadVFMulV", "ReadVFMulV", m.MX, e,
2811 SchedBinary<"WriteVFMulF", "ReadVFMulV", "ReadVFMulF", m.MX,
2819 defvar mx = m.MX;
2820 defvar sews = SchedSEWSet<mx, isF=1>.val;
2823 SchedBinary<"WriteVFDivV", "ReadVFDivV", "ReadVFDivV", mx, e,
2831 SchedBinary<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF", m.MX, f.SEW,
2841 SchedBinary<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF", m.MX, f.SEW,
2850 SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX,
2853 SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX,
2860 foreach e = SchedSEWSet<m.MX, isF=1>.val in
2862 SchedBinary<"WriteVFSgnjV", "ReadVFSgnjV", "ReadVFSgnjV", m.MX,
2869 SchedBinary<"WriteVFSgnjF", "ReadVFSgnjV", "ReadVFSgnjF", m.MX,
2877 foreach e = SchedSEWSet<m.MX, isF=1>.val in
2880 m.MX, e, forceMergeOpRead=true>;
2887 m.MX, f.SEW, forceMergeOpRead=true>;
2894 foreach e = SchedSEWSet<m.MX, isF=1>.val in
2896 SchedBinary<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV", m.MX, e,
2903 SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,
2913 SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,
2921 defvar mx = m.MX;
2923 SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,
2926 SchedUnary<"WriteVIALUI", "ReadVIALUV", mx, forceMergeOpRead=true>;
2932 defvar mx = m.MX;
2934 SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", mx,
2937 SchedBinary<"WriteVIWALUX", "ReadVIWALUV", "ReadVIWALUX", mx,
2944 defvar mx = m.MX;
2946 SchedBinary<"WriteVIWMulV", "ReadVIWMulV", "ReadVIWMulV", mx,
2949 SchedBinary<"WriteVIWMulX", "ReadVIWMulV", "ReadVIWMulX", mx,
2956 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
2958 SchedBinary<"WriteVFWMulV", "ReadVFWMulV", "ReadVFWMulV", m.MX,
2965 SchedBinary<"WriteVFWMulF", "ReadVFWMulV", "ReadVFWMulF", m.MX,
2973 defvar mx = m.MX;
2975 SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", mx,
2978 SchedBinary<"WriteVIWALUX", "ReadVIWALUV", "ReadVIWALUX", mx,
2985 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
2987 SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,
2994 SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX,
3002 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3004 SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,
3010 SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX,
3018 defvar mx = m.MX;
3019 def "_VVM" # "_" # m.MX:
3022 SchedBinary<"WriteVIMergeV", "ReadVIMergeV", "ReadVIMergeV", mx,
3024 def "_VXM" # "_" # m.MX:
3027 SchedBinary<"WriteVIMergeX", "ReadVIMergeV", "ReadVIMergeX", mx,
3029 def "_VIM" # "_" # m.MX:
3032 SchedUnary<"WriteVIMergeI", "ReadVIMergeV", mx,
3039 defvar mx = m.MX;
3041 SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
3044 SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
3047 SchedUnary<"WriteVICALUI", "ReadVICALUV", mx,
3054 defvar mx = m.MX;
3056 SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
3059 SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
3067 defvar mx = m.MX;
3070 SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
3073 SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
3076 SchedUnary<"WriteVICALUI", "ReadVICALUV", mx, forceMasked=1,
3084 defvar mx = m.MX;
3087 SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
3091 SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
3099 defvar mx = m.MX;
3102 SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
3105 SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
3108 SchedUnary<"WriteVICALUI", "ReadVICALUV", mx,
3116 defvar mx = m.MX;
3118 SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
3121 SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
3128 defvar mx = m.MX;
3130 SchedBinary<"WriteVNClipV", "ReadVNClipV", "ReadVNClipV", mx,
3133 SchedBinary<"WriteVNClipX", "ReadVNClipV", "ReadVNClipX", mx,
3136 SchedUnary<"WriteVNClipI", "ReadVNClipV", mx,
3143 defvar mx = m.MX;
3145 SchedBinary<"WriteVNShiftV", "ReadVNShiftV", "ReadVNShiftV", mx,
3148 SchedBinary<"WriteVNShiftX", "ReadVNShiftV", "ReadVNShiftX", mx,
3151 SchedUnary<"WriteVNShiftI", "ReadVNShiftV", mx,
3162 defvar mx = MInfo.MX;
3163 def "_" # mx # "_E" # sew : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class>;
3164 def "_" # mx # "_E" # sew # "_MASK" : VPseudoTernaryMaskPolicy<RetClass, Op1Class, Op2Class>,
3175 defvar mx = MInfo.MX;
3176 def "_" # mx # "_E" # sew
3179 def "_" # mx # "_E" # sew # "_MASK"
3195 def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint, TargetConstraintType>;
3196 def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint, TargetConstraintType>,
3210 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
3280 def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
3281 def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
3296 defvar mx = m.MX;
3299 "ReadVIMulAddV", mx>;
3302 "ReadVIMulAddV", mx>;
3308 foreach e = SchedSEWSet<m.MX, isF=1>.val in
3311 "ReadVFMulAddV", m.MX, e>;
3318 "ReadVFMulAddV", m.MX, f.SEW>;
3326 defvar mx = m.MX;
3329 "ReadVISlideX", mx>;
3331 SchedBinary<"WriteVSlideI", "ReadVISlideV", "ReadVISlideV", mx>;
3337 defvar mx = m.MX;
3340 "ReadVIWMulAddV", mx>;
3343 "ReadVIWMulAddV", mx>;
3351 "ReadVIWMulAddV", m.MX>;
3357 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3360 "ReadVFWMulAddV", "ReadVFWMulAddV", m.MX, e>;
3367 "ReadVFWMulAddF", "ReadVFWMulAddV", m.MX, f.SEW>;
3374 defvar mx = m.MX;
3375 foreach e = SchedSEWSet<mx, isF=1, isWidening=1>.val in
3378 "ReadVFWMulAddV", "ReadVFWMulAddV", mx, e>;
3383 defvar mx = m.MX;
3386 "ReadVFWMulAddF", "ReadVFWMulAddV", mx, f.SEW>;
3393 defvar mx = m.MX;
3395 SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;
3397 SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
3399 SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
3405 defvar mx = m.MX;
3407 SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;
3409 SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
3416 SchedBinary<"WriteVFCmpV", "ReadVFCmpV", "ReadVFCmpV", m.MX>;
3422 SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;
3431 SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;
3438 defvar mx = m.MX;
3440 SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
3442 SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
3448 defvar mx = m.MX;
3449 foreach e = SchedSEWSet<mx>.val in {
3451 SchedReduction<"WriteVIRedV_From", "ReadVIRedV", mx, e>;
3458 defvar mx = m.MX;
3459 foreach e = SchedSEWSet<mx>.val in {
3461 SchedReduction<"WriteVIRedMinMaxV_From", "ReadVIRedV", mx, e>;
3468 defvar mx = m.MX;
3469 foreach e = SchedSEWSet<mx, isWidening=1>.val in {
3471 SchedReduction<"WriteVIWRedV_From", "ReadVIWRedV", mx, e>;
3478 defvar mx = m.MX;
3479 foreach e = SchedSEWSet<mx, isF=1>.val in {
3483 SchedReduction<"WriteVFRedV_From", "ReadVFRedV", mx, e>;
3490 defvar mx = m.MX;
3491 foreach e = SchedSEWSet<mx, isF=1>.val in {
3493 SchedReduction<"WriteVFRedMinMaxV_From", "ReadVFRedV", mx, e>;
3500 defvar mx = m.MX;
3501 foreach e = SchedSEWSet<mx, isF=1>.val in {
3504 SchedReduction<"WriteVFRedOV_From", "ReadVFRedOV", mx, e>;
3511 defvar mx = m.MX;
3512 foreach e = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
3516 SchedReduction<"WriteVFWRedV_From", "ReadVFWRedV", mx, e>;
3523 defvar mx = m.MX;
3524 foreach e = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
3528 SchedReduction<"WriteVFWRedOV_From", "ReadVFWRedV", mx, e>;
3539 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
3555 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
3572 defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
3586 def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_NoExcept<RetClass, Op1Class, Constraint>;
3593 SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX,
3601 SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX,
3609 SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX,
3617 SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX,
3624 foreach e = SchedSEWSet<m.MX, isF=1>.val in
3626 SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, e,
3633 foreach e = SchedSEWSet<m.MX, isF=1>.val in
3635 SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, e,
3644 SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX,
3653 SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX,
3662 SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX,
3670 foreach e = SchedSEWSet<m.MX, isF=0, isWidening=1>.val in
3673 SchedUnary<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV", m.MX, e,
3681 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3684 SchedUnary<"WriteVFWCvtFToFV", "ReadVFWCvtFToFV", m.MX, e,
3693 SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX,
3702 SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX,
3711 SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX,
3719 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3723 SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, e,
3731 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3733 SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, e,
3741 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3744 SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, e,
3752 foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3756 SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, e,
3764 defvar LInfo = lmul.MX;
3781 defvar LInfo = lmul.MX;
3798 defvar LInfo = lmul.MX;
3820 defvar DataLInfo = dataEMUL.MX;
3847 defvar LInfo = lmul.MX;
3864 defvar LInfo = lmul.MX;
3886 defvar DataLInfo = dataEMUL.MX;
3910 //===----------------------------------------------------------------------===//
3912 //===----------------------------------------------------------------------===//
3930 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),
3931 inst#"_"#kind#"_"#vlmul.MX))
3953 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),
3954 inst#"_"#kind#"_"#vlmul.MX))
3977 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),
3978 inst#"_"#kind#"_"#vlmul.MX))
4001 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
4002 inst#"_"#kind#"_"#vlmul.MX#"_MASK"))
4026 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
4027 inst#"_"#kind#"_"#vlmul.MX#"_MASK"))
4053 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
4054 inst#"_"#kind#"_"#vlmul.MX#"_MASK"))
4098 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew))
4403 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew))
4426 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew))
4449 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
4474 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew),
4475 inst#"_"#kind#"_"#vlmul.MX))
4500 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK")
4528 inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew) # "_MASK",
4529 inst#"_"#kind#"_"#vlmul.MX # "_MASK"))
4555 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)# "_MASK")
4581 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)# "_MASK")
4683 (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX)
4688 (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_MASK")
4789 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
4812 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
4832 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
4901 instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
4902 instruction # "_VV_" # vti.LMul.MX),
4914 instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
4915 instruction # "_VV_" # vti.LMul.MX),
4927 instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
4944 defvar inst = instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
4962 instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW,
4963 instruction#"_"#kind#"_"#vti.LMul.MX),
4977 instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW,
4978 instruction#"_"#kind#"_"#vti.LMul.MX),
4989 defm : VPatBinary<intrinsic, instruction # "_VX_" # vti.LMul.MX,
4999 defm : VPatBinary<intrinsic, instruction # "_VI_" # vti.LMul.MX,
5011 instruction # "_VI_" # vti.LMul.MX,
5020 def : VPatBinaryM<intrinsic, instruction # "_MM_" # mti.LMul.MX,
5032 defm : VPatBinary<intrinsic, instruction # "_VV_" # Vti.LMul.MX,
5045 instruction # "_VV_" # Vti.LMul.MX # "_E" # Vti.SEW,
5046 instruction # "_VV_" # Vti.LMul.MX);
5064 defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
5078 instruction#"_"#kind#"_"#Vti.LMul.MX # "_E" # Vti.SEW,
5079 instruction#"_"#kind#"_"#Vti.LMul.MX);
5096 def : VPatTiedBinaryNoMask<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5099 def : VPatBinaryNoMaskTU<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5103 def : VPatTiedBinaryNoMaskTU<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5106 def : VPatTiedBinaryMask<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5110 def : VPatBinaryMaskPolicy<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5124 instruction # "_WV_" # Vti.LMul.MX # "_E" # Vti.SEW,
5125 instruction # "_WV_" # Vti.LMul.MX);
5158 defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
5172 instruction#"_"#kind#"_"#Vti.LMul.MX#"_E"#Vti.SEW,
5173 instruction#"_"#kind#"_"#Vti.LMul.MX);
5190 defm : VPatBinary<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5205 instruction # "_WV_" # Vti.LMul.MX,
5220 defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
5236 instruction#"_"#kind#"_"#Vti.LMul.MX,
5251 defm : VPatBinary<intrinsic, instruction # "_WI_" # Vti.LMul.MX,
5266 instruction # "_WI_" # Vti.LMul.MX,
5371 defm : VPatBinaryM<intrinsic, instruction # "_VV_" # vti.LMul.MX,
5381 defm : VPatBinaryMSwapped<intrinsic, instruction # "_VV_" # vti.LMul.MX,
5392 defm : VPatBinaryM<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX,
5403 defm : VPatBinaryM<intrinsic, instruction # "_VI_" # vti.LMul.MX,
6058 defvar Pseudo = !cast<Instruction>(inst#"_VI_"#vti.LMul.MX);
6066 defvar PseudoMask = !cast<Instruction>(inst#"_VI_"#vti.LMul.MX#"_MASK");
6078 //===----------------------------------------------------------------------===//
6080 //===----------------------------------------------------------------------===//
6084 //===----------------------------------------------------------------------===//
6086 //===----------------------------------------------------------------------===//
6105 def "PseudoVSPILL" # nf # "_" # lmul.MX :
6110 def "PseudoVRELOAD" # nf # "_" # lmul.MX :
6125 //===----------------------------------------------------------------------===//
6126 // 6. Configuration-Setting Instructions
6127 //===----------------------------------------------------------------------===//
6143 //===----------------------------------------------------------------------===//
6145 //===----------------------------------------------------------------------===//
6147 //===----------------------------------------------------------------------===//
6148 // 7.4 Vector Unit-Stride Instructions
6149 //===----------------------------------------------------------------------===//
6151 // Pseudos Unit-Stride Loads and Stores
6158 //===----------------------------------------------------------------------===//
6160 //===----------------------------------------------------------------------===//
6166 //===----------------------------------------------------------------------===//
6168 //===----------------------------------------------------------------------===//
6176 //===----------------------------------------------------------------------===//
6177 // 7.7. Unit-stride Fault-Only-First Loads
6178 //===----------------------------------------------------------------------===//
6184 //===----------------------------------------------------------------------===//
6186 //===----------------------------------------------------------------------===//
6201 //===----------------------------------------------------------------------===//
6203 //===----------------------------------------------------------------------===//
6205 //===----------------------------------------------------------------------===//
6206 // 11.1. Vector Single-Width Integer Add and Subtract
6207 //===----------------------------------------------------------------------===//
6222 (!cast<Instruction>("PseudoVSUB_VV_"#vti.LMul.MX)
6234 (!cast<Instruction>("PseudoVSUB_VV_"#vti.LMul.MX#"_MASK")
6248 (!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX)
6260 (!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX#"_MASK")
6271 //===----------------------------------------------------------------------===//
6273 //===----------------------------------------------------------------------===//
6283 //===----------------------------------------------------------------------===//
6285 //===----------------------------------------------------------------------===//
6293 //===----------------------------------------------------------------------===//
6294 // 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
6295 //===----------------------------------------------------------------------===//
6304 //===----------------------------------------------------------------------===//
6306 //===----------------------------------------------------------------------===//
6311 //===----------------------------------------------------------------------===//
6312 // 11.6. Vector Single-Width Bit Shift Instructions
6313 //===----------------------------------------------------------------------===//
6318 //===----------------------------------------------------------------------===//
6320 //===----------------------------------------------------------------------===//
6324 //===----------------------------------------------------------------------===//
6326 //===----------------------------------------------------------------------===//
6336 //===----------------------------------------------------------------------===//
6338 //===----------------------------------------------------------------------===//
6344 //===----------------------------------------------------------------------===//
6345 // 11.10. Vector Single-Width Integer Multiply Instructions
6346 //===----------------------------------------------------------------------===//
6352 //===----------------------------------------------------------------------===//
6354 //===----------------------------------------------------------------------===//
6360 //===----------------------------------------------------------------------===//
6362 //===----------------------------------------------------------------------===//
6367 //===----------------------------------------------------------------------===//
6368 // 11.13. Vector Single-Width Integer Multiply-Add Instructions
6369 //===----------------------------------------------------------------------===//
6375 //===----------------------------------------------------------------------===//
6376 // 11.14. Vector Widening Integer Multiply-Add Instructions
6377 //===----------------------------------------------------------------------===//
6383 //===----------------------------------------------------------------------===//
6385 //===----------------------------------------------------------------------===//
6388 //===----------------------------------------------------------------------===//
6390 //===----------------------------------------------------------------------===//
6393 //===----------------------------------------------------------------------===//
6394 // 12. Vector Fixed-Point Arithmetic Instructions
6395 //===----------------------------------------------------------------------===//
6397 //===----------------------------------------------------------------------===//
6398 // 12.1. Vector Single-Width Saturating Add and Subtract
6399 //===----------------------------------------------------------------------===//
6407 //===----------------------------------------------------------------------===//
6408 // 12.2. Vector Single-Width Averaging Add and Subtract
6409 //===----------------------------------------------------------------------===//
6415 //===----------------------------------------------------------------------===//
6416 // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
6417 //===----------------------------------------------------------------------===//
6422 //===----------------------------------------------------------------------===//
6423 // 12.4. Vector Single-Width Scaling Shift Instructions
6424 //===----------------------------------------------------------------------===//
6428 //===----------------------------------------------------------------------===//
6429 // 12.5. Vector Narrowing Fixed-Point Clip Instructions
6430 //===----------------------------------------------------------------------===//
6438 //===----------------------------------------------------------------------===//
6439 // 13. Vector Floating-Point Instructions
6440 //===----------------------------------------------------------------------===//
6443 //===----------------------------------------------------------------------===//
6444 // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
6445 //===----------------------------------------------------------------------===//
6452 //===----------------------------------------------------------------------===//
6453 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions
6454 //===----------------------------------------------------------------------===//
6462 //===----------------------------------------------------------------------===//
6463 // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
6464 //===----------------------------------------------------------------------===//
6471 //===----------------------------------------------------------------------===//
6472 // 13.5. Vector Widening Floating-Point Multiply
6473 //===----------------------------------------------------------------------===//
6478 //===----------------------------------------------------------------------===//
6479 // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
6480 //===----------------------------------------------------------------------===//
6492 //===----------------------------------------------------------------------===//
6493 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
6494 //===----------------------------------------------------------------------===//
6504 //===----------------------------------------------------------------------===//
6505 // 13.8. Vector Floating-Point Square-Root Instruction
6506 //===----------------------------------------------------------------------===//
6510 //===----------------------------------------------------------------------===//
6511 // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
6512 //===----------------------------------------------------------------------===//
6516 //===----------------------------------------------------------------------===//
6517 // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
6518 //===----------------------------------------------------------------------===//
6522 //===----------------------------------------------------------------------===//
6523 // 13.11. Vector Floating-Point Min/Max Instructions
6524 //===----------------------------------------------------------------------===//
6530 //===----------------------------------------------------------------------===//
6531 // 13.12. Vector Floating-Point Sign-Injection Instructions
6532 //===----------------------------------------------------------------------===//
6537 //===----------------------------------------------------------------------===//
6538 // 13.13. Vector Floating-Point Compare Instructions
6539 //===----------------------------------------------------------------------===//
6549 //===----------------------------------------------------------------------===//
6550 // 13.14. Vector Floating-Point Classify Instruction
6551 //===----------------------------------------------------------------------===//
6554 //===----------------------------------------------------------------------===//
6555 // 13.15. Vector Floating-Point Merge Instruction
6556 //===----------------------------------------------------------------------===//
6559 //===----------------------------------------------------------------------===//
6560 // 13.16. Vector Floating-Point Move Instruction
6561 //===----------------------------------------------------------------------===//
6564 //===----------------------------------------------------------------------===//
6565 // 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
6566 //===----------------------------------------------------------------------===//
6588 //===----------------------------------------------------------------------===//
6589 // 13.18. Widening Floating-Point/Integer Type-Convert Instructions
6590 //===----------------------------------------------------------------------===//
6609 //===----------------------------------------------------------------------===//
6610 // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
6611 //===----------------------------------------------------------------------===//
6639 //===----------------------------------------------------------------------===//
6641 //===----------------------------------------------------------------------===//
6644 //===----------------------------------------------------------------------===//
6645 // 14.1. Vector Single-Width Integer Reduction Instructions
6646 //===----------------------------------------------------------------------===//
6656 //===----------------------------------------------------------------------===//
6658 //===----------------------------------------------------------------------===//
6666 //===----------------------------------------------------------------------===//
6667 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
6668 //===----------------------------------------------------------------------===//
6678 //===----------------------------------------------------------------------===//
6679 // 14.4. Vector Widening Floating-Point Reduction Instructions
6680 //===----------------------------------------------------------------------===//
6689 //===----------------------------------------------------------------------===//
6691 //===----------------------------------------------------------------------===//
6694 //===----------------------------------------------------------------------===//
6695 // 15.1 Vector Mask-Register Logical Instructions
6696 //===----------------------------------------------------------------------===//
6711 //===----------------------------------------------------------------------===//
6713 //===----------------------------------------------------------------------===//
6717 //===----------------------------------------------------------------------===//
6718 // 15.3. vfirst find-first-set mask bit
6719 //===----------------------------------------------------------------------===//
6724 //===----------------------------------------------------------------------===//
6725 // 15.4. vmsbf.m set-before-first mask bit
6726 //===----------------------------------------------------------------------===//
6729 //===----------------------------------------------------------------------===//
6730 // 15.5. vmsif.m set-including-first mask bit
6731 //===----------------------------------------------------------------------===//
6734 //===----------------------------------------------------------------------===//
6735 // 15.6. vmsof.m set-only-first mask bit
6736 //===----------------------------------------------------------------------===//
6739 //===----------------------------------------------------------------------===//
6741 //===----------------------------------------------------------------------===//
6744 //===----------------------------------------------------------------------===//
6746 //===----------------------------------------------------------------------===//
6751 //===----------------------------------------------------------------------===//
6753 //===----------------------------------------------------------------------===//
6755 //===----------------------------------------------------------------------===//
6757 //===----------------------------------------------------------------------===//
6776 //===----------------------------------------------------------------------===//
6777 // 16.2. Floating-Point Scalar Move Instructions
6778 //===----------------------------------------------------------------------===//
6784 defvar mx = m.MX;
6787 def "PseudoVFMV_" # f.FX # "_S_" # mx :
6794 def "PseudoVFMV_S_" # f.FX # "_" # mx :
6807 //===----------------------------------------------------------------------===//
6809 //===----------------------------------------------------------------------===//
6822 //===----------------------------------------------------------------------===//
6824 //===----------------------------------------------------------------------===//
6829 //===----------------------------------------------------------------------===//
6831 //===----------------------------------------------------------------------===//
6835 //===----------------------------------------------------------------------===//
6837 //===----------------------------------------------------------------------===//
6839 //===----------------------------------------------------------------------===//
6841 //===----------------------------------------------------------------------===//
6843 //===----------------------------------------------------------------------===//
6844 // 11.1. Vector Single-Width Integer Add and Subtract
6845 //===----------------------------------------------------------------------===//
6850 //===----------------------------------------------------------------------===//
6852 //===----------------------------------------------------------------------===//
6862 //===----------------------------------------------------------------------===//
6864 //===----------------------------------------------------------------------===//
6878 //===----------------------------------------------------------------------===//
6879 // 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
6880 //===----------------------------------------------------------------------===//
6889 //===----------------------------------------------------------------------===//
6891 //===----------------------------------------------------------------------===//
6896 //===----------------------------------------------------------------------===//
6897 // 11.6. Vector Single-Width Bit Shift Instructions
6898 //===----------------------------------------------------------------------===//
6912 (!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX)
6921 (!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX#"_MASK")
6932 //===----------------------------------------------------------------------===//
6934 //===----------------------------------------------------------------------===//
6938 //===----------------------------------------------------------------------===//
6940 //===----------------------------------------------------------------------===//
6958 // Match vmslt(u).vx intrinsics to vmsle(u).vi if the scalar is -15 to 16 and
6959 // non-zero. Zero can be .vx with x0. This avoids the user needing to know that
6969 //===----------------------------------------------------------------------===//
6971 //===----------------------------------------------------------------------===//
6977 //===----------------------------------------------------------------------===//
6978 // 11.10. Vector Single-Width Integer Multiply Instructions
6979 //===----------------------------------------------------------------------===//
7002 //===----------------------------------------------------------------------===//
7004 //===----------------------------------------------------------------------===//
7010 //===----------------------------------------------------------------------===//
7012 //===----------------------------------------------------------------------===//
7017 //===----------------------------------------------------------------------===//
7018 // 11.13. Vector Single-Width Integer Multiply-Add Instructions
7019 //===----------------------------------------------------------------------===//
7025 //===----------------------------------------------------------------------===//
7026 // 11.14. Vector Widening Integer Multiply-Add Instructions
7027 //===----------------------------------------------------------------------===//
7033 //===----------------------------------------------------------------------===//
7035 //===----------------------------------------------------------------------===//
7038 //===----------------------------------------------------------------------===//
7040 //===----------------------------------------------------------------------===//
7046 (!cast<Instruction>("PseudoVMV_V_V_"#vti.LMul.MX)
7053 //===----------------------------------------------------------------------===//
7054 // 12. Vector Fixed-Point Arithmetic Instructions
7055 //===----------------------------------------------------------------------===//
7057 //===----------------------------------------------------------------------===//
7058 // 12.1. Vector Single-Width Saturating Add and Subtract
7059 //===----------------------------------------------------------------------===//
7065 //===----------------------------------------------------------------------===//
7066 // 12.2. Vector Single-Width Averaging Add and Subtract
7067 //===----------------------------------------------------------------------===//
7077 //===----------------------------------------------------------------------===//
7078 // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
7079 //===----------------------------------------------------------------------===//
7087 //===----------------------------------------------------------------------===//
7088 // 12.4. Vector Single-Width Scaling Shift Instructions
7089 //===----------------------------------------------------------------------===//
7095 //===----------------------------------------------------------------------===//
7096 // 12.5. Vector Narrowing Fixed-Point Clip Instructions
7097 //===----------------------------------------------------------------------===//
7103 //===----------------------------------------------------------------------===//
7104 // 13. Vector Floating-Point Instructions
7105 //===----------------------------------------------------------------------===//
7107 //===----------------------------------------------------------------------===//
7108 // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
7109 //===----------------------------------------------------------------------===//
7117 //===----------------------------------------------------------------------===//
7118 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions
7119 //===----------------------------------------------------------------------===//
7129 //===----------------------------------------------------------------------===//
7130 // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
7131 //===----------------------------------------------------------------------===//
7139 //===----------------------------------------------------------------------===//
7140 // 13.5. Vector Widening Floating-Point Multiply
7141 //===----------------------------------------------------------------------===//
7145 //===----------------------------------------------------------------------===//
7146 // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
7147 //===----------------------------------------------------------------------===//
7165 //===----------------------------------------------------------------------===//
7166 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
7167 //===----------------------------------------------------------------------===//
7180 //===----------------------------------------------------------------------===//
7181 // 13.8. Vector Floating-Point Square-Root Instruction
7182 //===----------------------------------------------------------------------===//
7185 //===----------------------------------------------------------------------===//
7186 // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
7187 //===----------------------------------------------------------------------===//
7190 //===----------------------------------------------------------------------===//
7191 // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
7192 //===----------------------------------------------------------------------===//
7195 //===----------------------------------------------------------------------===//
7196 // 13.11. Vector Floating-Point Min/Max Instructions
7197 //===----------------------------------------------------------------------===//
7203 //===----------------------------------------------------------------------===//
7204 // 13.12. Vector Floating-Point Sign-Injection Instructions
7205 //===----------------------------------------------------------------------===//
7213 //===----------------------------------------------------------------------===//
7214 // 13.13. Vector Floating-Point Compare Instructions
7215 //===----------------------------------------------------------------------===//
7225 //===----------------------------------------------------------------------===//
7226 // 13.14. Vector Floating-Point Classify Instruction
7227 //===----------------------------------------------------------------------===//
7230 //===----------------------------------------------------------------------===//
7231 // 13.15. Vector Floating-Point Merge Instruction
7232 //===----------------------------------------------------------------------===//
7233 // We can use vmerge.vvm to support vector-vector vfmerge.
7234 // NOTE: Clang previously used int_riscv_vfmerge for vector-vector, but now uses
7258 defvar instr = !cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX);
7268 //===----------------------------------------------------------------------===//
7269 // 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
7270 //===----------------------------------------------------------------------===//
7282 //===----------------------------------------------------------------------===//
7283 // 13.18. Widening Floating-Point/Integer Type-Convert Instructions
7284 //===----------------------------------------------------------------------===//
7300 //===----------------------------------------------------------------------===//
7301 // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
7302 //===----------------------------------------------------------------------===//
7328 //===----------------------------------------------------------------------===//
7330 //===----------------------------------------------------------------------===//
7332 //===----------------------------------------------------------------------===//
7333 // 14.1. Vector Single-Width Integer Reduction Instructions
7334 //===----------------------------------------------------------------------===//
7344 //===----------------------------------------------------------------------===//
7346 //===----------------------------------------------------------------------===//
7350 //===----------------------------------------------------------------------===//
7351 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
7352 //===----------------------------------------------------------------------===//
7358 //===----------------------------------------------------------------------===//
7359 // 14.4. Vector Widening Floating-Point Reduction Instructions
7360 //===----------------------------------------------------------------------===//
7364 //===----------------------------------------------------------------------===//
7366 //===----------------------------------------------------------------------===//
7368 //===----------------------------------------------------------------------===//
7369 // 15.1 Vector Mask-Register Logical Instructions
7370 //===----------------------------------------------------------------------===//
7384 //===----------------------------------------------------------------------===//
7386 //===----------------------------------------------------------------------===//
7389 //===----------------------------------------------------------------------===//
7390 // 15.3. vfirst find-first-set mask bit
7391 //===----------------------------------------------------------------------===//
7394 //===----------------------------------------------------------------------===//
7395 // 15.4. vmsbf.m set-before-first mask bit
7396 //===----------------------------------------------------------------------===//
7399 //===----------------------------------------------------------------------===//
7400 // 15.5. vmsif.m set-including-first mask bit
7401 //===----------------------------------------------------------------------===//
7404 //===----------------------------------------------------------------------===//
7405 // 15.6. vmsof.m set-only-first mask bit
7406 //===----------------------------------------------------------------------===//
7409 //===----------------------------------------------------------------------===//
7411 //===----------------------------------------------------------------------===//
7414 //===----------------------------------------------------------------------===//
7416 //===----------------------------------------------------------------------===//
7420 //===----------------------------------------------------------------------===//
7422 //===----------------------------------------------------------------------===//
7424 //===----------------------------------------------------------------------===//
7426 //===----------------------------------------------------------------------===//
7435 //===----------------------------------------------------------------------===//
7437 //===----------------------------------------------------------------------===//
7448 //===----------------------------------------------------------------------===//
7450 //===----------------------------------------------------------------------===//
7460 //===----------------------------------------------------------------------===//
7462 //===----------------------------------------------------------------------===//
7466 // Include the non-intrinsic ISel patterns