Lines Matching refs:rd
518 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPRMem:$rs1, simm12:$imm12),
519 opcodestr, "$rd, ${imm12}(${rs1})">;
522 : RVInstR<funct7, 0b100, OPC_SYSTEM, (outs GPR:$rd),
523 (ins GPRMemZeroOffset:$rs1), opcodestr, "$rd, $rs1"> {
541 let rd = 0;
547 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
548 opcodestr, "$rd, $rs1, $imm12">,
553 : RVInstIShift<imm11_7, funct3, OPC_OP_IMM, (outs GPR:$rd),
555 "$rd, $rs1, $shamt">,
561 : RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
562 opcodestr, "$rd, $rs1, $rs2"> {
569 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
570 opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
575 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
577 opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR]>;
581 : RVInstIShiftW<imm11_5, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
583 "$rd, $rs1, $shamt">,
589 : RVInstR<funct7, funct3, OPC_OP_32, (outs GPR:$rd),
590 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
603 let rd = 0;
613 def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20),
614 "lui", "$rd, $imm20">, Sched<[WriteIALU]>;
616 def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20),
617 "auipc", "$rd, $imm20">, Sched<[WriteIALU]>;
619 def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20),
620 "jal", "$rd, $imm20">, Sched<[WriteJal]>;
622 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
624 "jalr", "$rd, ${imm12}(${rs1})">,
699 let rd = 0;
705 let rd = 0;
711 let rd = 0;
717 let rd = 0;
724 let rd = 0;
734 let rd = 0;
757 def ADDIW : RVInstI<0b000, OPC_OP_IMM_32, (outs GPR:$rd),
759 "addiw", "$rd, $rs1, $imm12">,
785 let rd = 0;
791 let rd = 0;
798 let rd = 0;
805 let rd = 0;
811 let rd = 0;
849 let rd = 0;
867 def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm_li:$imm), [],
868 "li", "$rd, $imm">;
886 def : InstAlias<"li $rd, $imm", (ADDI GPR:$rd, X0, simm12:$imm)>;
887 def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>;
888 def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>;
889 def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>;
892 def : InstAlias<"negw $rd, $rs", (SUBW GPR:$rd, X0, GPR:$rs)>;
893 def : InstAlias<"sext.w $rd, $rs", (ADDIW GPR:$rd, GPR:$rs, 0)>;
896 def : InstAlias<"seqz $rd, $rs", (SLTIU GPR:$rd, GPR:$rs, 1)>;
897 def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>;
898 def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>;
899 def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>;
903 def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>;
904 def : InstAlias<"sgtu $rd, $rs, $rt", (SLTU GPR:$rd, GPR:$rt, GPR:$rs), 0>;
941 def : InstAlias<"jalr $rd, $rs", (JALR GPR:$rd, GPR:$rs, 0), 2>;
947 def : InstAlias<"jalr $rd, $rs, $offset", (JALR GPR:$rd, GPR:$rs, simm12:$offset), 0>;
950 def : InstAlias<"jalr $rd, (${rs})", (JALR GPR:$rd, GPR:$rs, 0), 0>;
957 def : InstAlias<"rdinstret $rd", (CSRRS GPR:$rd, INSTRET.Encoding, X0)>;
958 def : InstAlias<"rdcycle $rd", (CSRRS GPR:$rd, CYCLE.Encoding, X0)>;
959 def : InstAlias<"rdtime $rd", (CSRRS GPR:$rd, TIME.Encoding, X0)>;
962 def : InstAlias<"rdinstreth $rd", (CSRRS GPR:$rd, INSTRETH.Encoding, X0)>;
963 def : InstAlias<"rdcycleh $rd", (CSRRS GPR:$rd, CYCLEH.Encoding, X0)>;
964 def : InstAlias<"rdtimeh $rd", (CSRRS GPR:$rd, TIMEH.Encoding, X0)>;
967 def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr, X0)>;
981 def : InstAlias<"csrrw $rd, $csr, $imm", (CSRRWI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
982 def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
983 def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
1003 def : InstAlias<"lb $rd, (${rs1})",
1004 (LB GPR:$rd, GPR:$rs1, 0)>;
1005 def : InstAlias<"lh $rd, (${rs1})",
1006 (LH GPR:$rd, GPR:$rs1, 0)>;
1007 def : InstAlias<"lw $rd, (${rs1})",
1008 (LW GPR:$rd, GPR:$rs1, 0)>;
1009 def : InstAlias<"lbu $rd, (${rs1})",
1010 (LBU GPR:$rd, GPR:$rs1, 0)>;
1011 def : InstAlias<"lhu $rd, (${rs1})",
1012 (LHU GPR:$rd, GPR:$rs1, 0)>;
1021 def : InstAlias<"add $rd, $rs1, $imm12",
1022 (ADDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1023 def : InstAlias<"and $rd, $rs1, $imm12",
1024 (ANDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1025 def : InstAlias<"xor $rd, $rs1, $imm12",
1026 (XORI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1027 def : InstAlias<"or $rd, $rs1, $imm12",
1028 (ORI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1029 def : InstAlias<"sll $rd, $rs1, $shamt",
1030 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1031 def : InstAlias<"srl $rd, $rs1, $shamt",
1032 (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1033 def : InstAlias<"sra $rd, $rs1, $shamt",
1034 (SRAI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1036 def : InstAlias<"lwu $rd, (${rs1})",
1037 (LWU GPR:$rd, GPR:$rs1, 0)>;
1038 def : InstAlias<"ld $rd, (${rs1})",
1039 (LD GPR:$rd, GPR:$rs1, 0)>;
1043 def : InstAlias<"addw $rd, $rs1, $imm12",
1044 (ADDIW GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1045 def : InstAlias<"sllw $rd, $rs1, $shamt",
1046 (SLLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
1047 def : InstAlias<"srlw $rd, $rs1, $shamt",
1048 (SRLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
1049 def : InstAlias<"sraw $rd, $rs1, $shamt",
1050 (SRAIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
1052 def : InstAlias<"slt $rd, $rs1, $imm12",
1053 (SLTI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1054 def : InstAlias<"sltu $rd, $rs1, $imm12",
1055 (SLTIU GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1069 def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>;
1093 def InsnR : DirectiveInsnR<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode, uimm3:$funct3,
1096 "$opcode, $funct3, $funct7, $rd, $rs1, $rs2">;
1097 def InsnR4 : DirectiveInsnR4<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
1102 "$opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3">;
1103 def InsnI : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode, uimm3:$funct3,
1105 "$opcode, $funct3, $rd, $rs1, $imm12">;
1106 def InsnI_Mem : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
1110 "$opcode, $funct3, $rd, ${imm12}(${rs1})">;
1115 def InsnU : DirectiveInsnU<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
1117 "$opcode, $rd, $imm20">;
1118 def InsnJ : DirectiveInsnJ<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
1120 "$opcode, $rd, $imm20">;
1138 def : InstAlias<".insn_r $opcode, $funct3, $funct7, $rd, $rs1, $rs2",
1139 (InsnR AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3, uimm7:$funct7,
1142 def : InstAlias<".insn_r $opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3",
1143 (InsnR4 AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3, uimm2:$funct2,
1145 def : InstAlias<".insn_r4 $opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3",
1146 (InsnR4 AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3, uimm2:$funct2,
1148 def : InstAlias<".insn_i $opcode, $funct3, $rd, $rs1, $imm12",
1149 (InsnI AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1,
1151 def : InstAlias<".insn_i $opcode, $funct3, $rd, ${imm12}(${rs1})",
1152 (InsnI_Mem AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3,
1154 def : InstAlias<".insn_i $opcode, $funct3, $rd, (${rs1})",
1155 (InsnI_Mem AnyReg:$rd, uimm7_opcode:$opcode, uimm3:$funct3,
1164 def : InstAlias<".insn_u $opcode, $rd, $imm20",
1165 (InsnU AnyReg:$rd, uimm7_opcode:$opcode, uimm20_lui:$imm20)>;
1166 def : InstAlias<".insn_j $opcode, $rd, $imm20",
1167 (InsnJ AnyReg:$rd, uimm7_opcode:$opcode, simm21_lsb0_jal:$imm20)>;
1169 def : InstAlias<".insn_uj $opcode, $rd, $imm20",
1170 (InsnJ AnyReg:$rd, uimm7_opcode:$opcode, simm21_lsb0_jal:$imm20)>;
1286 // is never compressible since rs1 and rd can't be the same register.
1320 def PseudoAddTPRel : Pseudo<(outs GPR:$rd),
1322 "add", "$rd, $rs1, $rs2, $src">;
1528 def PseudoCALLReg : Pseudo<(outs GPR:$rd), (ins call_symbol:$func), [],
1529 "call", "$rd, $func">,
1591 def PseudoJump : Pseudo<(outs GPR:$rd), (ins pseudo_jump_symbol:$target), [],
1592 "jump", "$target, $rd">,
1633 def PseudoLAImm : Pseudo<(outs GPR:$rd), (ins ixlenimm_li_restricted:$imm), [],
1634 "la", "$rd, $imm">;
1667 def PseudoTLSDESCCall : Pseudo<(outs GPR:$rd),
1669 "jalr", "$rd, ${imm12}(${rs1}), $src">,
1682 def PseudoSEXT_B : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "sext.b", "$rd, $rs">;
1683 def PseudoSEXT_H : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "sext.h", "$rd, $rs">;
1686 def PseudoZEXT_H : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.h", "$rd, $rs">;
1691 def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs">;
1747 : Pseudo<(outs GPR:$rd), (ins),
1748 [(set GPR:$rd, (XLenVT (riscv_read_csr (XLenVT SR.Encoding))))]>,
1749 PseudoInstExpansion<(CSRRS GPR:$rd, SR.Encoding, X0)> {
1771 : Pseudo<(outs GPR:$rd), (ins GPR:$val),
1772 [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), (XLenVT GPR:$val)))]>,
1773 PseudoInstExpansion<(CSRRW GPR:$rd, SR.Encoding, GPR:$val)> {
1780 : Pseudo<(outs GPR:$rd), (ins uimm5:$val),
1781 [(set GPR:$rd, (XLenVT (riscv_swap_csr (XLenVT SR.Encoding), uimm5:$val)))]>,
1782 PseudoInstExpansion<(CSRRWI GPR:$rd, SR.Encoding, uimm5:$val)> {