Lines Matching full:override

67   MCInst getNop() const override;
71                                int &FrameIndex) const override;
73                                unsigned &MemBytes) const override;
75                               int &FrameIndex) const override;
77                               unsigned &MemBytes) const override;
79   bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
87                    bool KillSrc) const override;
94                            Register VReg) const override;
100                             Register VReg) const override;
108                                       VirtRegMap *VRM = nullptr) const override;
116   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
121                      bool AllowModify) const override;
126                         int *BytesAdded = nullptr) const override;
131                             int64_t BrOffset, RegScavenger *RS) const override;
134                         int *BytesRemoved = nullptr) const override;
137   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
139   bool optimizeCondBranch(MachineInstr &MI) const override;
141   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
144                              int64_t BrOffset) const override;
148                      unsigned &FalseOp, bool &Optimizable) const override;
152                                bool) const override;
154   bool isAsCheapAsAMove(const MachineInstr &MI) const override;
157   isCopyInstrImpl(const MachineInstr &MI) const override;
160                          StringRef &ErrInfo) const override;
164                            ExtAddrMode &AM) const override;
167                                  const ExtAddrMode &AM) const override;
172       const TargetRegisterInfo *TRI) const override;
179                            unsigned NumBytes) const override;
187                                        const MachineInstr &MIb) const override;
191   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
194   getSerializableDirectMachineOperandTargetFlags() const override;
198                                    bool OutlineFromLinkOnceODRs) const override;
203                               unsigned &Flags) const override;
205   bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
209       std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
214                        unsigned Flags) const override;
218                           const outliner::OutlinedFunction &OF) const override;
224                      outliner::Candidate &C) const override;
227                                            Register Reg) const override;
230                              unsigned &SrcOpIdx2) const override;
233                                        unsigned OpIdx2) const override;
236                                       LiveIntervals *LIS) const override;
242                           const TargetRegisterInfo *TRI) const override;
251   bool useMachineCombiner() const override { return true; }  in useMachineCombiner()
253   MachineTraceStrategy getMachineCombinerTraceStrategy() const override;
255   CombinerObjective getCombinerObjective(unsigned Pattern) const override;
259                                   bool DoRegPressureReduce) const override;
263                     SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
269       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
272                                const MachineBasicBlock *MBB) const override;
275                               bool &Commuted) const override;
278                                    bool Invert) const override;
280   std::optional<unsigned> getInverseOpcode(unsigned Opcode) const override;
284       std::array<unsigned, 5> &OperandIndices) const override;
287   getSerializableMachineMemOperandTargetFlags() const override;
289   unsigned getUndefInitOpcode(unsigned RegClassID) const override {  in getUndefInitOpcode()