188   bool computeVXRMChanges(const MachineBasicBlock &MBB);
189   void computeAvailable(const MachineBasicBlock &MBB);
190   void computeAnticipated(const MachineBasicBlock &MBB);
191   void emitWriteVXRM(MachineBasicBlock &MBB);
211 bool RISCVInsertWriteVXRM::computeVXRMChanges(const MachineBasicBlock &MBB) {  in computeVXRMChanges()  argument
212   BlockData &BBInfo = BlockInfo[MBB.getNumber()];  in computeVXRMChanges()
215   for (const MachineInstr &MI : MBB) {  in computeVXRMChanges()
240 void RISCVInsertWriteVXRM::computeAvailable(const MachineBasicBlock &MBB) {  in computeAvailable()  argument
241   BlockData &BBInfo = BlockInfo[MBB.getNumber()];  in computeAvailable()
246   if (MBB.pred_empty()) {  in computeAvailable()
249     for (const MachineBasicBlock *P : MBB.predecessors())  in computeAvailable()
259     LLVM_DEBUG(dbgs() << "AvailableIn state of " << printMBBReference(MBB)  in computeAvailable()
270   LLVM_DEBUG(dbgs() << "AvailableOut state of " << printMBBReference(MBB)  in computeAvailable()
274   for (MachineBasicBlock *S : MBB.successors()) {  in computeAvailable()
282 void RISCVInsertWriteVXRM::computeAnticipated(const MachineBasicBlock &MBB) {  in computeAnticipated()  argument
283   BlockData &BBInfo = BlockInfo[MBB.getNumber()];  in computeAnticipated()
288   if (MBB.succ_empty()) {  in computeAnticipated()
291     for (const MachineBasicBlock *S : MBB.successors())  in computeAnticipated()
302     LLVM_DEBUG(dbgs() << "AnticipatedOut state of " << printMBBReference(MBB)  in computeAnticipated()
314   LLVM_DEBUG(dbgs() << "AnticipatedIn state of " << printMBBReference(MBB)  in computeAnticipated()
318   for (MachineBasicBlock *P : MBB.predecessors()) {  in computeAnticipated()
326 void RISCVInsertWriteVXRM::emitWriteVXRM(MachineBasicBlock &MBB) {  in emitWriteVXRM()  argument
327   const BlockData &BBInfo = BlockInfo[MBB.getNumber()];  in emitWriteVXRM()
338     if (MBB.isEntryBlock()) {  in emitWriteVXRM()
346       for (MachineBasicBlock *P : MBB.predecessors()) {  in emitWriteVXRM()
368   for (MachineInstr &MI : MBB) {  in emitWriteVXRM()
379         BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteVXRMImm))  in emitWriteVXRM()
408     LLVM_DEBUG(dbgs() << "Inserting at end of " << printMBBReference(MBB)  in emitWriteVXRM()
410     BuildMI(MBB, MBB.getFirstTerminator(), DebugLoc(),  in emitWriteVXRM()
429   for (const MachineBasicBlock &MBB : MF)  in runOnMachineFunction()  local
430     NeedVXRMChange |= computeVXRMChanges(MBB);  in runOnMachineFunction()
438   for (const MachineBasicBlock &MBB : MF) {  in runOnMachineFunction()  local
439     WorkList.push(&MBB);  in runOnMachineFunction()
440     BlockInfo[MBB.getNumber()].InQueue = true;  in runOnMachineFunction()
443     const MachineBasicBlock &MBB = *WorkList.front();  in runOnMachineFunction()  local
445     computeAvailable(MBB);  in runOnMachineFunction()
449   for (const MachineBasicBlock &MBB : llvm::reverse(MF)) {  in runOnMachineFunction()  local
450     WorkList.push(&MBB);  in runOnMachineFunction()
451     BlockInfo[MBB.getNumber()].InQueue = true;  in runOnMachineFunction()
454     const MachineBasicBlock &MBB = *WorkList.front();  in runOnMachineFunction()  local
456     computeAnticipated(MBB);  in runOnMachineFunction()
460   for (MachineBasicBlock &MBB : MF)  in runOnMachineFunction()
461     emitWriteVXRM(MBB);  in runOnMachineFunction()