Lines Matching +full:csr +full:- +full:2 +full:l

1 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that RISC-V uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
30 // clang-format off
37   /// Select with condition operator - This selects between a true value and
40   /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
57   // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
68   // RV64I shifts, directly matching the semantics of the named RISC-V
73   // 32-bit operations from RV64M that can't be simply matched with a pattern
79   // RV64IB rotates, directly matching the semantics of the named RISC-V
84   // named RISC-V instructions.
91   // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
95   // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
96   // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
98   // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
101   // unnecessary GPR->FPR->GPR moves.
107   // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
132   // Floating point fmax and fmin matching the RISC-V instruction semantics.
135   // A read of the 64-bit counter CSR on a 32-bit target (returns (Lo, Hi)).
137   // CSR numbers of the low and high parts of the counter).
153   // May-Be-Operations
177   // Splats an 64-bit value that has been split into two i32 parts. This is
181   // Truncates a RVV integer vector by one power-of-two. Carries both an extra
185   // pass-thru operand, the second is the source vector, the third is the XLenVT
186   // index (either constant or non-constant), the fourth is the mask, the fifth
204   // Matches the semantics of the vfcnvt.rod function (Convert double-width
205   // float to single-width float, rounding towards odd). Takes a double-width
206   // float vector and produces a single-width float vector. Also has a mask and
212   // third vector operand. The first operand is the pass-thru operand. The
214   // third operand's types are expected to be the corresponding full-width
388   // Read VLENB CSR
390   // Reads value of CSR.
392   // required CSR. Two results are produced, the read value and the new chain
395   // Write value to CSR.
397   // required CSR and the third is the value to write. The result is the new
400   // Read and write value of CSR.
402   // required CSR and the third is the value to write. Two results are produced,
478 // clang-format on
561     // save two bitwise instructions and one float-to-int instruction and  in isMultiStoresCheaperThanBitsMerge()
563     // significant benefit because it avoids the float->int domain switch  in isMultiStoresCheaperThanBitsMerge()
728   /// with the clang -ffixed-xX flag for access to be allowed.
894   /// RISCVCCAssignFn - This target-specific function extends the default
895   /// CCValAssign with additional information used to lower RISC-V calling
1026   /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR.
1050 /// 2. For vector data arguments or rest vector mask arguments, starting from
1051 /// the v8 register, if a vector register group between v8-v23 that has not been
1057 /// NFIELDS consecutive vector register groups between v8-v23 that have not been