Lines Matching defs:LMUL
166 // Disable the smallest fractional LMUL types if ELEN is less than
1554 // The maximum VF is for the smallest element width with LMUL=8.
2457 llvm_unreachable("Invalid LMUL.");
2478 llvm_unreachable("Invalid LMUL.");
2494 RISCVII::VLMUL LMUL = getLMUL(VT);
2495 if (LMUL == RISCVII::VLMUL::LMUL_F8 ||
2496 LMUL == RISCVII::VLMUL::LMUL_F4 ||
2497 LMUL == RISCVII::VLMUL::LMUL_F2 ||
2498 LMUL == RISCVII::VLMUL::LMUL_1) {
2503 if (LMUL == RISCVII::VLMUL::LMUL_2) {
2508 if (LMUL == RISCVII::VLMUL::LMUL_4) {
2538 // LMUL>1 register class down to the outgoing one. At each step we half
2539 // the LMUL:
2705 // We prefer to use LMUL=1 for VLEN sized types. Use fractional lmuls for
2706 // narrower types. The smallest fractional LMUL we support is 8/ELEN. Within
2707 // each fractional LMUL we support SEW between 8 and LMUL*ELEN.
2876 /// is generally quadratic in the number of vreg implied by LMUL. Note that
2883 /// vrgather.vi/vx may be linear in the number of vregs implied by LMUL,
2891 /// variants.) Slides may be linear in the number of vregs implied by LMUL,
2899 /// variants.) Slides may be linear in the number of vregs implied by LMUL,
3894 // Our main goal here is to reduce LMUL (and thus work) required to
4151 // being (at least) linear in LMUL. As a result, using the vslidedown
4152 // lowering for every element ends up being VL*LMUL..
5296 // may involve vector splitting if we're already at LMUL=8, or our
5297 // user-supplied maximum fixed-length LMUL.
5314 // requires less work and less register pressure at high LMUL, and creates
6881 // perform the vslideups at a smaller LMUL, limited to MF2.
8158 // the LMUL will be sufficient to hold the smaller type.
8415 // smallest subvector that the index fits in. This can be used to reduce LMUL
8471 // we're performing the scalar inserts and slideup on a smaller LMUL.
8477 // Do we know an upper bound on LMUL?
8713 // Reduce the LMUL of our slidedown and vmv.x.s to the smallest LMUL which
8733 // is linear in LMUL, performing N extracts using vslidedown becomes
8735 // seems to have the same problem (the store is linear in LMUL), but the
8861 SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT);
8867 LMUL);
8876 SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT);
8884 SEW, LMUL);
8949 // fractional LMULs. The LMUL is choosen so that with SEW=8 the VLMax is
8952 // SEW and LMUL are better for the surrounding vector instructions.
8957 // The smallest LMUL is only valid for the smallest element width.
8960 // Determine the VF that corresponds to LMUL 1 for ElementWidth.
9071 // LMUL * VLEN should be greater than or equal to EGS * SEW
10062 // don't know which register of a LMUL group contains the specific subvector
10161 // We do this by lowering to an EXTRACT_SUBVECTOR grabbing the nearest LMUL=1
10164 // of that LMUL=1 type back into the larger vector (resolving to another
10166 // LMUL=1 type to avoid allocating a large register group to hold our
10305 // don't know which register of a LMUL group contains the specific subvector
10315 // Shrink down Vec so we're performing the slidedown on a smaller LMUL.
10388 // If the vector type is an LMUL-group type, extract a subvector equal to the
10392 // If VecVT has an LMUL > 1, then SubVecVT should have a smaller LMUL, and
10462 // If the VT is LMUL=8, we need to split and reassemble.
10541 // If the VT is LMUL=8, we need to split and reassemble.
10646 // TODO: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
10671 // If this is LMUL=8, we have to split before can use vrgatherei16.vv.
10690 // Just promote the int type to i16 which will double the LMUL.
11693 // NOTE: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
11695 // If this is LMUL=8, we have to split before using vrgatherei16.vv.
11738 // Just promote the int type to i16 which will double the LMUL.
14120 // work and less register pressure at high LMUL, and creates smaller constants
18542 // Helper to find Masked Pseudo instruction from MC instruction, LMUL and SEW.
18547 assert(Inverse && "Unexpected LMUL and SEW pair for instruction");
18550 assert(Masked && "Could not find masked instruction for LMUL and SEW pair");
21446 // operations to correspond roughly to that threshold. LMUL>1 operations
21449 // combining will typically form larger LMUL operations from the LMUL1
21651 auto [LMUL, Fractional] = RISCVVType::decodeVLMUL(getLMUL(ContainerVT));
21654 return Factor * LMUL <= 8;