Lines Matching +defs:U +defs:Z
2164 if (!Op || any_of(Ops, [&](Use *U) { return U->get() == Op; }))
2178 for (Use &U : Op->uses()) {
2179 Instruction *Insn = cast<Instruction>(U.getUser());
2180 if (!canSplatOperand(Insn, U.getOperandNo()))
6967 // Using getSetCCSwappedOperands will convert SET(U)GT->SET(U)LT.
12352 auto MakeMULPair = [&](SDValue S, SDValue U) {
12355 U = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, U);
12356 SDValue Lo = DAG.getNode(ISD::MUL, DL, XLenVT, S, U);
12357 SDValue Hi = DAG.getNode(RISCVISD::MULHSU, DL, XLenVT, S, U);
14155 NewElen = std::max(NewElen, 8U);
14562 // i1 types are legal but we can't select V{S,Z}EXT_VLs with them.
15109 SDValue Z = MergeOp->getOperand(2);
15111 if (Z.getOpcode() == ISD::INSERT_SUBVECTOR &&
15112 (isNullOrNullSplat(Z.getOperand(0)) || Z.getOperand(0).isUndef()))
15113 Z = Z.getOperand(1);
15115 if (!ISD::isConstantSplatVectorAllZeros(Z.getNode()))
15663 for (SDNode *U : N0->uses()) {
15664 if (U->getOpcode() != ISD::SRA ||
15665 !isa<ConstantSDNode>(U->getOperand(1)) ||
15666 U->getConstantOperandVal(1) > 32)
15712 // Invert (and/or (set cc X, Y), (xor Z, 1)) to (or/and (set !cc X, Y)), Z) if
15714 // inverting the setcc is free, and Z is 0/1. Caller will invert the
15735 // (xor Z, 1) to (not Z).
18308 // C: Z = PHI [X, A], [Y, B]
18310 // E: PHI [X, C], [Z, D]
20676 return std::make_pair(0U, &RISCV::GPRF16RegClass);
20678 return std::make_pair(0U, &RISCV::GPRF32RegClass);
20680 return std::make_pair(0U, &RISCV::GPRPairRegClass);
20681 return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
20684 return std::make_pair(0U, &RISCV::FPR16RegClass);
20686 return std::make_pair(0U, &RISCV::FPR32RegClass);
20688 return std::make_pair(0U, &RISCV::FPR64RegClass);
20697 return std::make_pair(0U, RC);
20701 return std::make_pair(0U, &RISCV::VMV0RegClass);
22110 Type *ElemTy = STy->getTypeAtIndex(0U);