1 //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines an instruction selector for the RISC-V target.
11 //===----------------------------------------------------------------------===//
21 // RISC-V specific code to select RISC-V machine instructions for
72         if (C && C->getZExtValue() == maskTrailingOnes<uint64_t>(Bits)) {  in SelectAddrRegZextRegScale()
87   bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
88   bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt) {  in selectShiftMaskXLen()  argument
89     return selectShiftMask(N, Subtarget->getXLen(), ShAmt);  in selectShiftMaskXLen()
91   bool selectShiftMask32(SDValue N, SDValue &ShAmt) {  in selectShiftMask32()  argument
92     return selectShiftMask(N, 32, ShAmt);  in selectShiftMask32()
95   bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val);
96   bool selectSETNE(SDValue N, SDValue &Val) {  in selectSETNE()  argument
97     return selectSETCC(N, ISD::SETNE, Val);  in selectSETNE()
99   bool selectSETEQ(SDValue N, SDValue &Val) {  in selectSETEQ()  argument
100     return selectSETCC(N, ISD::SETEQ, Val);  in selectSETEQ()
103   bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val);
104   template <unsigned Bits> bool selectSExtBits(SDValue N, SDValue &Val) {  in selectSExtBits()  argument
105     return selectSExtBits(N, Bits, Val);  in selectSExtBits()
107   bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val);
108   template <unsigned Bits> bool selectZExtBits(SDValue N, SDValue &Val) {  in selectZExtBits()  argument
109     return selectZExtBits(N, Bits, Val);  in selectZExtBits()
112   bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val);
113   template <unsigned ShAmt> bool selectSHXADDOp(SDValue N, SDValue &Val) {  in selectSHXADDOp()  argument
114     return selectSHXADDOp(N, ShAmt, Val);  in selectSHXADDOp()
117   bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val);
118   template <unsigned ShAmt> bool selectSHXADD_UWOp(SDValue N, SDValue &Val) {  in selectSHXADD_UWOp()  argument
119     return selectSHXADD_UWOp(N, ShAmt, Val);  in selectSHXADD_UWOp()
128   bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2);
130   bool selectVLOp(SDValue N, SDValue &VL);
132   bool selectVSplat(SDValue N, SDValue &SplatVal);
133   bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
134   bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal);
135   template <unsigned Bits> bool selectVSplatUimmBits(SDValue N, SDValue &Val) {  in selectVSplatUimmBits()  argument
136     return selectVSplatUimm(N, Bits, Val);  in selectVSplatUimmBits()
138   bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
139   bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal);
142   bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal);
143   bool selectFPImm(SDValue N, SDValue &Imm);
145   bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
146   template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {  in selectRVVSimm5()  argument
147     return selectRVVSimm5(N, Width, Imm);  in selectRVVSimm5()
166   // Return the RISC-V condition code that matches the given DAG integer
167   // condition code. The CondCode must be one of those supported by the RISC-V
196   bool performCombineVMergeAndVOps(SDNode *N);
212   uint16_t Log2SEW : 3;
213   uint16_t LMUL : 3;
221   uint16_t Log2SEW : 3;
222   uint16_t LMUL : 3;
223   uint16_t IndexLMUL : 3;
231   uint16_t Log2SEW : 3;
232   uint16_t LMUL : 3;
240   uint16_t Log2SEW : 3;
241   uint16_t LMUL : 3;
242   uint16_t IndexLMUL : 3;
250   uint16_t Log2SEW : 3;
251   uint16_t LMUL : 3;
258   uint16_t Log2SEW : 3;
259   uint16_t LMUL : 3;
266   uint16_t Log2SEW : 3;
267   uint16_t LMUL : 3;
268   uint16_t IndexLMUL : 3;