Lines Matching refs:Width

53                          bool IsMasked, int Width,
57                             AtomicRMWInst::BinOp, bool IsMasked, int Width,
61                            int Width, MachineBasicBlock::iterator &NextMBBI);
241 static unsigned getLRForRMW(AtomicOrdering Ordering, int Width,
243   if (Width == 32)
245   if (Width == 64)
250 static unsigned getSCForRMW(AtomicOrdering Ordering, int Width,
252   if (Width == 32)
254   if (Width == 64)
263                                    AtomicRMWInst::BinOp BinOp, int Width,
277   BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg)
291   BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)), ScratchReg)
327                                          AtomicRMWInst::BinOp BinOp, int Width,
329   assert(Width == 32 && "Should never need to expand masked 64-bit operations");
390     AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
411     doAtomicBinOpExpansion(TII, MI, DL, &MBB, LoopMBB, DoneMBB, BinOp, Width,
415                                  Width, STI);
440     AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
444   assert(Width == 32 && "Should never need to expand masked 64-bit operations");
627     int Width, MachineBasicBlock::iterator &NextMBBI) {
667     BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)),
677     BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)),
691     BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)),
710     BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)),