Lines Matching +full:ouput +full:- +full:only
1 //===-- RISCVAsmPrinter.cpp - RISC-V LLVM assembly writer -----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // of machine-dependent LLVM code to the RISC-V assembly language.
12 //===----------------------------------------------------------------------===//
47 #define DEBUG_TYPE "asm-printer"
50 "Number of RISC-V Compressed instructions emitted");
65 StringRef getPassName() const override { return "RISC-V Assembly Printer"; } in getPassName()
116 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4; in LowerSTACKMAP()
132 if (MII == MBB.end() || MII->isCall() || in LowerSTACKMAP()
133 MII->getOpcode() == RISCV::DBG_VALUE || in LowerSTACKMAP()
134 MII->getOpcode() == TargetOpcode::PATCHPOINT || in LowerSTACKMAP()
135 MII->getOpcode() == TargetOpcode::STACKMAP) in LowerSTACKMAP()
138 NumNOPBytes -= 4; in LowerSTACKMAP()
149 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4; in LowerPATCHPOINT()
191 assert((NumBytes - EncodedBytes) % NOPBytes == 0 && in LowerPATCHPOINT()
193 emitNops((NumBytes - EncodedBytes) / NOPBytes); in LowerPATCHPOINT()
198 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4; in LowerSTATEPOINT()
251 // Simple pseudo-instructions have their lowering (with expansion to real
252 // instructions) auto-generated.
258 if (!STI->hasStdExtZihintntl()) in emitNTLHint()
261 if (MI->memoperands_empty()) in emitNTLHint()
264 MachineMemOperand *MMO = *(MI->memoperands_begin()); in emitNTLHint()
265 if (!MMO->isNonTemporal()) in emitNTLHint()
269 if (MMO->getFlags() & MONontemporalBit0) in emitNTLHint()
271 if (MMO->getFlags() & MONontemporalBit1) in emitNTLHint()
275 if (STI->hasStdExtCOrZca() && STI->enableRVCHintInstrs()) in emitNTLHint()
288 RISCV_MC::verifyInstructionPredicates(MI->getOpcode(), in emitInstruction()
293 // Do any auto-generated pseudo lowerings. in emitInstruction()
298 switch (MI->getOpcode()) { in emitInstruction()
329 const MachineOperand &MO = MI->getOperand(OpNo); in PrintAsmOperand()
362 Sym->print(OS, MAI); in PrintAsmOperand()
379 const MachineOperand &AddrReg = MI->getOperand(OpNo); in PrintAsmMemoryOperand()
380 assert(MI->getNumOperands() > OpNo + 1 && "Expected additional operand"); in PrintAsmMemoryOperand()
381 const MachineOperand &Offset = MI->getOperand(OpNo + 1); in PrintAsmMemoryOperand()
404 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer()); in emitDirectiveOptionArch()
408 if (STI->hasFeature(Feature.Value) == MCSTI.hasFeature(Feature.Value)) in emitDirectiveOptionArch()
414 auto Delta = STI->hasFeature(Feature.Value) ? RISCVOptionArchArgType::Plus in emitDirectiveOptionArch()
430 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer()); in runOnMachineFunction()
444 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer()); in emitStartOfAsmFile()
446 dyn_cast_or_null<MDString>(M.getModuleFlag("target-abi"))) in emitStartOfAsmFile()
447 RTS.setTargetABI(RISCVABI::getTargetABI(ModuleTargetABI->getString())); in emitStartOfAsmFile()
452 if (auto *MD = dyn_cast_or_null<MDNode>(M.getModuleFlag("riscv-isa"))) { in emitStartOfAsmFile()
453 for (auto &ISA : MD->operands()) { in emitStartOfAsmFile()
456 ISAString->getString(), /*EnableExperimentalExtension=*/true, in emitStartOfAsmFile()
461 if (ISAInfo->hasExtension(Feature.Key) && in emitStartOfAsmFile()
478 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer()); in emitEndOfAsmFile()
487 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer()); in emitAttributes()
495 const auto *RMFI = MF->getInfo<RISCVMachineFunctionInfo>(); in emitFunctionEntryLabel()
496 if (RMFI->isVectorCall()) { in emitFunctionEntryLabel()
498 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer()); in emitFunctionEntryLabel()
516 // FIXME: Make this work on non-ELF. in LowerHWASAN_CHECK_MEMACCESS()
518 report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF"); in LowerHWASAN_CHECK_MEMACCESS()
520 std::string SymName = "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" + in LowerHWASAN_CHECK_MEMACCESS()
532 assert(std::next(MI.getIterator())->isCall() && in LowerKCFI_CHECK()
534 assert(std::next(MI.getIterator())->getOperand(0).getReg() == AddrReg && in LowerKCFI_CHECK()
540 // call. The check defaults to X6/X7, but can fall back to X28-X31 if in LowerKCFI_CHECK()
545 return Reg != AddrReg && !STI->isRegisterReservedByUser(Reg); in LowerKCFI_CHECK()
565 // Adjust the offset for patchable-function-prefix. This assumes that in LowerKCFI_CHECK()
566 // patchable-function-prefix is the same for all functions. in LowerKCFI_CHECK()
567 int NopSize = STI->hasStdExtCOrZca() ? 2 : 4; in LowerKCFI_CHECK()
570 ->getFunction() in LowerKCFI_CHECK()
571 .getFnAttribute("patchable-function-prefix") in LowerKCFI_CHECK()
579 .addImm(-(PrefixNops * NopSize + 4))); in LowerKCFI_CHECK()
582 // Load the expected 32-bit type hash. in LowerKCFI_CHECK()
593 MCInstBuilder((STI->hasFeature(RISCV::Feature64Bit) && Hi20) in LowerKCFI_CHECK()
610 OutStreamer->emitLabel(Trap); in LowerKCFI_CHECK()
613 OutStreamer->emitLabel(Pass); in LowerKCFI_CHECK()
629 // run-time linkers can instead eagerly bind this function. in EmitHwasanMemaccessSymbols()
631 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer()); in EmitHwasanMemaccessSymbols()
646 OutStreamer->switchSection(OutContext.getELFSection( in EmitHwasanMemaccessSymbols()
648 ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, 0, Sym->getName(), in EmitHwasanMemaccessSymbols()
651 OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction); in EmitHwasanMemaccessSymbols()
652 OutStreamer->emitSymbolAttribute(Sym, MCSA_Weak); in EmitHwasanMemaccessSymbols()
653 OutStreamer->emitSymbolAttribute(Sym, MCSA_Hidden); in EmitHwasanMemaccessSymbols()
654 OutStreamer->emitLabel(Sym); in EmitHwasanMemaccessSymbols()
657 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
660 OutStreamer->emitInstruction(MCInstBuilder(RISCV::SRLI) in EmitHwasanMemaccessSymbols()
666 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADD) in EmitHwasanMemaccessSymbols()
671 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
675 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
680 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
688 OutStreamer->emitLabel(ReturnSym); in EmitHwasanMemaccessSymbols()
689 OutStreamer->emitInstruction(MCInstBuilder(RISCV::JALR) in EmitHwasanMemaccessSymbols()
694 OutStreamer->emitLabel(HandleMismatchOrPartialSym); in EmitHwasanMemaccessSymbols()
696 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
702 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
709 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
714 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
717 .addImm(Size - 1), in EmitHwasanMemaccessSymbols()
719 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
726 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
729 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
732 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
739 OutStreamer->emitLabel(HandleMismatchSym); in EmitHwasanMemaccessSymbols()
742 // +=================================+ <-- [SP + 256] in EmitHwasanMemaccessSymbols()
745 // | Stack frame space for x12 - x31.| in EmitHwasanMemaccessSymbols()
748 // +---------------------------------+ <-- [SP + 96] in EmitHwasanMemaccessSymbols()
751 // +---------------------------------+ <-- [SP + 88] in EmitHwasanMemaccessSymbols()
754 // +---------------------------------+ <-- [SP + 80] in EmitHwasanMemaccessSymbols()
757 // +---------------------------------+ <-- [SP + 72] in EmitHwasanMemaccessSymbols()
761 // +---------------------------------+ <-- [SP + 64] in EmitHwasanMemaccessSymbols()
764 // | Stack frame space for x2 - x7. | in EmitHwasanMemaccessSymbols()
767 // +---------------------------------+ <-- [SP + 16] in EmitHwasanMemaccessSymbols()
770 // +---------------------------------+ <-- [SP + 8] in EmitHwasanMemaccessSymbols()
773 // +---------------------------------+ <-- [x2 / SP] in EmitHwasanMemaccessSymbols()
776 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
779 .addImm(-256), in EmitHwasanMemaccessSymbols()
783 OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD) in EmitHwasanMemaccessSymbols()
789 OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD) in EmitHwasanMemaccessSymbols()
796 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
801 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
806 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
811 OutStreamer->emitInstruction( in EmitHwasanMemaccessSymbols()
818 OutStreamer->emitInstruction(MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr), in EmitHwasanMemaccessSymbols()
911 MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), *this); in lowerOperand()
940 RISCVVPseudosTable::getPseudoInfo(MI->getOpcode()); in lowerRISCVVMachineInstrToMCInst()
944 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst()
946 const MachineBasicBlock *MBB = MI->getParent(); in lowerRISCVVMachineInstrToMCInst()
948 const MachineFunction *MF = MBB->getParent(); in lowerRISCVVMachineInstrToMCInst()
951 const RISCVSubtarget &Subtarget = MF->getSubtarget<RISCVSubtarget>(); in lowerRISCVVMachineInstrToMCInst()
956 const MCInstrDesc &MCID = MI->getDesc(); in lowerRISCVVMachineInstrToMCInst()
958 unsigned NumOps = MI->getNumExplicitOperands(); in lowerRISCVVMachineInstrToMCInst()
963 --NumOps; in lowerRISCVVMachineInstrToMCInst()
965 --NumOps; in lowerRISCVVMachineInstrToMCInst()
967 --NumOps; in lowerRISCVVMachineInstrToMCInst()
969 --NumOps; in lowerRISCVVMachineInstrToMCInst()
973 const MachineOperand &MO = MI->getOperand(OpNo); in lowerRISCVVMachineInstrToMCInst()
974 // Skip vl ouput. It should be the second output. in lowerRISCVVMachineInstrToMCInst()
979 if (OpNo == MI->getNumExplicitDefs() && MO.isReg() && MO.isTied()) { in lowerRISCVVMachineInstrToMCInst()
982 const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode()); in lowerRISCVVMachineInstrToMCInst()
1001 Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0); in lowerRISCVVMachineInstrToMCInst()
1005 TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass); in lowerRISCVVMachineInstrToMCInst()
1008 Reg = TRI->getSubReg(Reg, RISCV::sub_32); in lowerRISCVVMachineInstrToMCInst()
1021 Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0); in lowerRISCVVMachineInstrToMCInst()
1037 const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode()); in lowerRISCVVMachineInstrToMCInst()
1041 "Expected only mask operand to be missing"); in lowerRISCVVMachineInstrToMCInst()
1053 OutMI.setOpcode(MI->getOpcode()); in lowerToMCInst()
1055 for (const MachineOperand &MO : MI->operands()) { in lowerToMCInst()
1063 const Function &F = MI->getParent()->getParent()->getFunction(); in lowerToMCInst()
1064 if (F.hasFnAttribute("patchable-function-entry")) { in lowerToMCInst()
1066 if (F.getFnAttribute("patchable-function-entry") in lowerToMCInst()