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1 //===-- PPCScheduleE500mc.td - e5500 Scheduling Defs -------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the itinerary class data for the Freescale e5500 64-bit
13 // Freescale Document Number e5500RM, Rev. 1, 03/2012.
15 //===----------------------------------------------------------------------===//
20 // Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
27 // The CFX has a bypass path, allowing non-divide instructions to execute
30 def E5500_SFX1 : FuncUnit; // Simple unit 1
36 def E5500_CFX_1 : FuncUnit; // CFX pipeline stage 1
50 InstrItinData<IIC_IntSimple, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
51 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
52 [5, 2, 2], // Latency = 1
55 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
56 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
57 [5, 2, 2], // Latency = 1
60 InstrItinData<IIC_IntISEL, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
61 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
62 [5, 2, 2, 2], // Latency = 1
66 InstrItinData<IIC_IntCompare, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
67 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
68 [6, 2, 2], // Latency = 1 or 2
71 InstrItinData<IIC_IntDivD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
72 InstrStage<1, [E5500_CFX_0], 0>,
74 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
77 InstrItinData<IIC_IntDivW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
78 InstrStage<1, [E5500_CFX_0], 0>,
80 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
83 InstrItinData<IIC_IntMFFS, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
84 InstrStage<1, [E5500_FPU_0]>],
85 [11], // Latency = 7, Repeat rate = 1
87 InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
89 [11, 2, 2], // Latency = 7, Repeat rate = 7
91 InstrItinData<IIC_IntMulHD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
92 InstrStage<1, [E5500_CFX_0], 0>,
93 InstrStage<2, [E5500_CFX_1]>],
94 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
97 InstrItinData<IIC_IntMulHW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
98 InstrStage<1, [E5500_CFX_0], 0>,
99 InstrStage<1, [E5500_CFX_1]>],
100 [8, 2, 2], // Latency = 4, Repeat rate = 1
103 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
104 InstrStage<1, [E5500_CFX_0], 0>,
105 InstrStage<1, [E5500_CFX_1]>],
106 [8, 2, 2], // Latency = 4, Repeat rate = 1
109 InstrItinData<IIC_IntMulLI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
110 InstrStage<1, [E5500_CFX_0], 0>,
111 InstrStage<2, [E5500_CFX_1]>],
112 [8, 2, 2], // Latency = 4 or 5, Repeat = 2
115 InstrItinData<IIC_IntRotate, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
116 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
117 [5, 2, 2], // Latency = 1
120 InstrItinData<IIC_IntRotateD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
121 InstrStage<2, [E5500_SFX0, E5500_SFX1]>],
122 [6, 2, 2], // Latency = 2, Repeat rate = 2
125 InstrItinData<IIC_IntRotateDI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
126 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
127 [5, 2, 2], // Latency = 1, Repeat rate = 1
130 InstrItinData<IIC_IntShift, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
131 InstrStage<2, [E5500_SFX0, E5500_SFX1]>],
132 [6, 2, 2], // Latency = 2, Repeat rate = 2
135 InstrItinData<IIC_IntTrapW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
136 InstrStage<2, [E5500_SFX0]>],
137 [6, 2], // Latency = 2, Repeat rate = 2
139 InstrItinData<IIC_BrB, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
140 InstrStage<1, [E5500_BU]>],
141 [5, 2], // Latency = 1
143 InstrItinData<IIC_BrCR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
144 InstrStage<1, [E5500_BU]>],
145 [5, 2, 2], // Latency = 1
148 InstrItinData<IIC_BrMCR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
149 InstrStage<1, [E5500_BU]>],
150 [5, 2], // Latency = 1
152 InstrItinData<IIC_BrMCRX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
153 InstrStage<1, [E5500_CFX_0]>],
154 [5, 2, 2], // Latency = 1
156 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
157 InstrStage<1, [E5500_LSU_0]>],
158 [7, 2], // Latency = 3, Repeat rate = 1
160 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
161 InstrStage<1, [E5500_LSU_0]>],
162 [7, 2], // Latency = 3, Repeat rate = 1
164 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
165 InstrStage<1, [E5500_LSU_0]>],
166 [7, 2], // Latency = 3, Repeat rate = 1
168 InstrItinData<IIC_LdStLoad, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
169 InstrStage<1, [E5500_LSU_0]>],
170 [7, 2], // Latency = 3
172 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
173 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
174 InstrStage<1, [E5500_LSU_0]>],
175 [7, 2], // Latency = 3, Repeat rate = 1
177 2>, // 2 micro-ops
178 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
179 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
180 InstrStage<1, [E5500_LSU_0]>],
181 [7, 2], // Latency = 3, Repeat rate = 1
183 2>, // 2 micro-ops
184 InstrItinData<IIC_LdStLD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
185 InstrStage<1, [E5500_LSU_0]>],
186 [7, 2], // Latency = 3, Repeat rate = 1
188 InstrItinData<IIC_LdStLDARX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
190 [7, 2], // Latency = 3, Repeat rate = 3
192 InstrItinData<IIC_LdStLDU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
193 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
194 InstrStage<1, [E5500_LSU_0]>],
195 [7, 2], // Latency = 3, Repeat rate = 1
197 2>, // 2 micro-ops
198 InstrItinData<IIC_LdStLDUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
199 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
200 InstrStage<1, [E5500_LSU_0]>],
201 [7, 2], // Latency = 3, Repeat rate = 1
203 2>, // 2 micro-ops
204 InstrItinData<IIC_LdStStore, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
205 InstrStage<1, [E5500_LSU_0]>],
206 [7, 2], // Latency = 3, Repeat rate = 1
208 InstrItinData<IIC_LdStICBI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
209 InstrStage<1, [E5500_LSU_0]>],
210 [7, 2], // Latency = 3, Repeat rate = 1
212 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
213 InstrStage<1, [E5500_LSU_0]>],
214 [7, 2, 2], // Latency = 3, Repeat rate = 1
217 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
218 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
219 InstrStage<1, [E5500_LSU_0]>],
220 [7, 2, 2], // Latency = 3, Repeat rate = 1
223 2>, // 2 micro-ops
224 InstrItinData<IIC_LdStLFD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
225 InstrStage<1, [E5500_LSU_0]>],
226 [8, 2, 2], // Latency = 4, Repeat rate = 1
229 2>, // 2 micro-ops
230 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
231 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
232 InstrStage<1, [E5500_LSU_0]>],
233 [8, 2, 2], // Latency = 4, Repeat rate = 1
236 2>, // 2 micro-ops
237 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
238 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
239 InstrStage<1, [E5500_LSU_0]>],
240 [8, 2, 2], // Latency = 4, Repeat rate = 1
243 2>, // 2 micro-ops
244 InstrItinData<IIC_LdStLHA, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
245 InstrStage<1, [E5500_LSU_0]>],
246 [7, 2], // Latency = 3
248 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
249 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
250 InstrStage<1, [E5500_LSU_0]>],
251 [7, 2], // Latency = 3, Repeat rate = 1
253 2>, // 2 micro-ops
254 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
255 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
256 InstrStage<1, [E5500_LSU_0]>],
257 [7, 2], // Latency = 3, Repeat rate = 1
259 2>, // 2 micro-ops
260 InstrItinData<IIC_LdStLMW, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
262 [8, 2], // Latency = r+3, Repeat rate = r+3
264 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
266 [7, 2, 2], // Latency = 3, Repeat rate = 3
269 InstrItinData<IIC_LdStSTD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
270 InstrStage<1, [E5500_LSU_0]>],
271 [7, 2], // Latency = 3, Repeat rate = 1
273 InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
274 InstrStage<1, [E5500_LSU_0]>],
275 [7, 2], // Latency = 3, Repeat rate = 1
277 InstrItinData<IIC_LdStSTU, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
278 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
279 InstrStage<1, [E5500_LSU_0]>],
280 [7, 2], // Latency = 3, Repeat rate = 1
282 2>, // 2 micro-ops
283 InstrItinData<IIC_LdStSTUX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
284 InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
285 InstrStage<1, [E5500_LSU_0]>],
286 [7, 2], // Latency = 3, Repeat rate = 1
288 2>, // 2 micro-ops
289 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
290 InstrStage<1, [E5500_LSU_0]>],
291 [7, 2], // Latency = 3, Repeat rate = 1
293 InstrItinData<IIC_LdStSync, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
294 InstrStage<1, [E5500_LSU_0]>]>,
295 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
296 InstrStage<2, [E5500_CFX_0]>],
297 [6, 2], // Latency = 2, Repeat rate = 4
299 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
300 InstrStage<1, [E5500_LSU_0], 0>]>,
301 InstrItinData<IIC_SprMFCR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
303 [9, 2], // Latency = 5, Repeat rate = 5
305 InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
307 [9, 2], // Latency = 5, Repeat rate = 5
309 InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
311 [8, 2], // Latency = 4, Repeat rate = 4
313 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
314 InstrStage<1, [E5500_CFX_0]>],
315 [5], // Latency = 1, Repeat rate = 1
317 InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
318 InstrStage<1, [E5500_CFX_0]>],
319 [5], // Latency = 1, Repeat rate = 1
321 InstrItinData<IIC_SprMFTB, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
323 [8, 2], // Latency = 4, Repeat rate = 4
325 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
326 InstrStage<1, [E5500_CFX_0]>],
327 [5], // Latency = 1, Repeat rate = 1
329 InstrItinData<IIC_FPGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
330 InstrStage<1, [E5500_FPU_0]>],
331 [11, 2, 2], // Latency = 7, Repeat rate = 1
334 InstrItinData<IIC_FPAddSub, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
335 InstrStage<1, [E5500_FPU_0]>],
336 [11, 2, 2], // Latency = 7, Repeat rate = 1
339 InstrItinData<IIC_FPCompare, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
340 InstrStage<1, [E5500_FPU_0]>],
341 [11, 2, 2], // Latency = 7, Repeat rate = 1
344 InstrItinData<IIC_FPDivD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
346 [39, 2, 2], // Latency = 35, Repeat rate = 31
349 InstrItinData<IIC_FPDivS, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
351 [24, 2, 2], // Latency = 20, Repeat rate = 16
354 InstrItinData<IIC_FPFused, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
355 InstrStage<1, [E5500_FPU_0]>],
356 [11, 2, 2, 2], // Latency = 7, Repeat rate = 1
360 InstrItinData<IIC_FPRes, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
361 InstrStage<2, [E5500_FPU_0]>],
362 [12, 2], // Latency = 8, Repeat rate = 2
366 // ===---------------------------------------------------------------------===//
370 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.