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1 //===-- PPCScheduleE500mc.td - e5500 Scheduling Defs -------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the itinerary class data for the Freescale e5500 64-bit
15 //===----------------------------------------------------------------------===//
20 // Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
27 // The CFX has a bypass path, allowing non-divide instructions to execute
52 [5, 2, 2], // Latency = 1
57 [5, 2, 2], // Latency = 1
62 [5, 2, 2, 2], // Latency = 1
68 [6, 2, 2], // Latency = 1 or 2
74 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
80 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
89 [11, 2, 2], // Latency = 7, Repeat rate = 7
93 InstrStage<2, [E5500_CFX_1]>],
94 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
100 [8, 2, 2], // Latency = 4, Repeat rate = 1
106 [8, 2, 2], // Latency = 4, Repeat rate = 1
111 InstrStage<2, [E5500_CFX_1]>],
112 [8, 2, 2], // Latency = 4 or 5, Repeat = 2
117 [5, 2, 2], // Latency = 1
121 InstrStage<2, [E5500_SFX0, E5500_SFX1]>],
122 [6, 2, 2], // Latency = 2, Repeat rate = 2
127 [5, 2, 2], // Latency = 1, Repeat rate = 1
131 InstrStage<2, [E5500_SFX0, E5500_SFX1]>],
132 [6, 2, 2], // Latency = 2, Repeat rate = 2
136 InstrStage<2, [E5500_SFX0]>],
137 [6, 2], // Latency = 2, Repeat rate = 2
141 [5, 2], // Latency = 1
145 [5, 2, 2], // Latency = 1
150 [5, 2], // Latency = 1
154 [5, 2, 2], // Latency = 1
158 [7, 2], // Latency = 3, Repeat rate = 1
162 [7, 2], // Latency = 3, Repeat rate = 1
166 [7, 2], // Latency = 3, Repeat rate = 1
170 [7, 2], // Latency = 3
175 [7, 2], // Latency = 3, Repeat rate = 1
177 2>, // 2 micro-ops
181 [7, 2], // Latency = 3, Repeat rate = 1
183 2>, // 2 micro-ops
186 [7, 2], // Latency = 3, Repeat rate = 1
190 [7, 2], // Latency = 3, Repeat rate = 3
195 [7, 2], // Latency = 3, Repeat rate = 1
197 2>, // 2 micro-ops
201 [7, 2], // Latency = 3, Repeat rate = 1
203 2>, // 2 micro-ops
206 [7, 2], // Latency = 3, Repeat rate = 1
210 [7, 2], // Latency = 3, Repeat rate = 1
214 [7, 2, 2], // Latency = 3, Repeat rate = 1
220 [7, 2, 2], // Latency = 3, Repeat rate = 1
223 2>, // 2 micro-ops
226 [8, 2, 2], // Latency = 4, Repeat rate = 1
229 2>, // 2 micro-ops
233 [8, 2, 2], // Latency = 4, Repeat rate = 1
236 2>, // 2 micro-ops
240 [8, 2, 2], // Latency = 4, Repeat rate = 1
243 2>, // 2 micro-ops
246 [7, 2], // Latency = 3
251 [7, 2], // Latency = 3, Repeat rate = 1
253 2>, // 2 micro-ops
257 [7, 2], // Latency = 3, Repeat rate = 1
259 2>, // 2 micro-ops
262 [8, 2], // Latency = r+3, Repeat rate = r+3
266 [7, 2, 2], // Latency = 3, Repeat rate = 3
271 [7, 2], // Latency = 3, Repeat rate = 1
275 [7, 2], // Latency = 3, Repeat rate = 1
280 [7, 2], // Latency = 3, Repeat rate = 1
282 2>, // 2 micro-ops
286 [7, 2], // Latency = 3, Repeat rate = 1
288 2>, // 2 micro-ops
291 [7, 2], // Latency = 3, Repeat rate = 1
296 InstrStage<2, [E5500_CFX_0]>],
297 [6, 2], // Latency = 2, Repeat rate = 4
303 [9, 2], // Latency = 5, Repeat rate = 5
307 [9, 2], // Latency = 5, Repeat rate = 5
311 [8, 2], // Latency = 4, Repeat rate = 4
323 [8, 2], // Latency = 4, Repeat rate = 4
331 [11, 2, 2], // Latency = 7, Repeat rate = 1
336 [11, 2, 2], // Latency = 7, Repeat rate = 1
341 [11, 2, 2], // Latency = 7, Repeat rate = 1
346 [39, 2, 2], // Latency = 35, Repeat rate = 31
351 [24, 2, 2], // Latency = 20, Repeat rate = 16
356 [11, 2, 2, 2], // Latency = 7, Repeat rate = 1
361 InstrStage<2, [E5500_FPU_0]>],
362 [12, 2], // Latency = 8, Repeat rate = 2
366 // ===---------------------------------------------------------------------===//
370 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.