Lines Matching full:ppc
32 #include "PPC.h"
52 #define DEBUG_TYPE "ppc-mi-peepholes"
64 "Number of functions entered in PPC MI Peepholes");
76 FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true),
81 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true),
85 EnableSExtElimination("ppc-eliminate-signext",
90 EnableZExtElimination("ppc-eliminate-zeroext",
95 EnableTrapOptimization("ppc-opt-conditional-trap",
100 PeepholeXToICounter, "ppc-xtoi-peephole",
101 "Controls whether PPC reg+reg to reg+imm peephole is performed on a MI");
103 DEBUG_COUNTER(PeepholePerOpCounter, "ppc-per-op-peephole",
104 "Controls whether PPC per opcode peephole is performed on a MI");
148 BuildMI(MBB, At, At->getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), Reg); in addDummyDef()
174 assert((MF.getRegInfo().use_empty(PPC::X2) || in runOnMachineFunction()
183 "-mllvm -disable-ppc-peephole"); in runOnMachineFunction()
234 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || in getKnownLeadingZeroCount()
235 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec) in getKnownLeadingZeroCount()
238 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && in getKnownLeadingZeroCount()
242 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in getKnownLeadingZeroCount()
243 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || in getKnownLeadingZeroCount()
244 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in getKnownLeadingZeroCount()
248 if (Opcode == PPC::ANDI_rec) { in getKnownLeadingZeroCount()
253 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec || in getKnownLeadingZeroCount()
254 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec || in getKnownLeadingZeroCount()
255 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8) in getKnownLeadingZeroCount()
259 if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec || in getKnownLeadingZeroCount()
260 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec) in getKnownLeadingZeroCount()
264 if (Opcode == PPC::LHZ || Opcode == PPC::LHZX || in getKnownLeadingZeroCount()
265 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || in getKnownLeadingZeroCount()
266 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || in getKnownLeadingZeroCount()
267 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8) in getKnownLeadingZeroCount()
270 if (Opcode == PPC::LBZ || Opcode == PPC::LBZX || in getKnownLeadingZeroCount()
271 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || in getKnownLeadingZeroCount()
272 Opcode == PPC::LBZU || Opcode == PPC::LBZUX || in getKnownLeadingZeroCount()
273 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8) in getKnownLeadingZeroCount()
276 if (Opcode == PPC::AND || Opcode == PPC::AND8 || Opcode == PPC::AND_rec || in getKnownLeadingZeroCount()
277 Opcode == PPC::AND8_rec) in getKnownLeadingZeroCount()
282 if (Opcode == PPC::OR || Opcode == PPC::OR8 || Opcode == PPC::XOR || in getKnownLeadingZeroCount()
283 Opcode == PPC::XOR8 || Opcode == PPC::OR_rec || in getKnownLeadingZeroCount()
284 Opcode == PPC::OR8_rec || Opcode == PPC::XOR_rec || in getKnownLeadingZeroCount()
285 Opcode == PPC::XOR8_rec) in getKnownLeadingZeroCount()
370 if (Opcode == PPC::COPY) { in collectUnprimedAccPHIs()
372 if (!Reg.isVirtual() || MRI->getRegClass(Reg) != &PPC::ACCRCRegClass) in collectUnprimedAccPHIs()
374 } else if (Opcode != PPC::IMPLICIT_DEF && Opcode != PPC::PHI) in collectUnprimedAccPHIs()
380 if (Opcode != PPC::PHI) in collectUnprimedAccPHIs()
410 assert((Opcode == PPC::COPY || Opcode == PPC::IMPLICIT_DEF || in convertUnprimedAccPHIs()
411 Opcode == PPC::PHI) && in convertUnprimedAccPHIs()
413 if (Opcode == PPC::COPY) { in convertUnprimedAccPHIs()
415 &PPC::ACCRCRegClass && in convertUnprimedAccPHIs()
418 } else if (Opcode == PPC::IMPLICIT_DEF) { in convertUnprimedAccPHIs()
419 Register AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass); in convertUnprimedAccPHIs()
421 TII->get(PPC::IMPLICIT_DEF), AccReg); in convertUnprimedAccPHIs()
424 } else if (Opcode == PPC::PHI) { in convertUnprimedAccPHIs()
443 AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass); in convertUnprimedAccPHIs()
445 *PHI->getParent(), PHI, PHI->getDebugLoc(), TII->get(PPC::PHI), AccReg); in convertUnprimedAccPHIs()
526 MO.setReg(PPC::NoRegister); in simplifyCode()
563 case PPC::COPY: { in simplifyCode()
568 if (MRI->getRegClass(Src) != &PPC::UACCRCRegClass || in simplifyCode()
569 MRI->getRegClass(Dst) != &PPC::ACCRCRegClass) in simplifyCode()
582 if (RootPHI->getOpcode() != PPC::PHI) in simplifyCode()
594 case PPC::LI: in simplifyCode()
595 case PPC::LI8: { in simplifyCode()
598 // PPC::ZERO. in simplifyCode()
614 case PPC::STW: in simplifyCode()
615 case PPC::STD: { in simplifyCode()
628 case PPC::XXPERMDI: { in simplifyCode()
663 if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS) in simplifyCode()
669 if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX) in simplifyCode()
675 (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat())) { in simplifyCode()
679 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
689 if (DefOpc == PPC::XXPERMDI) { in simplifyCode()
709 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
739 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
748 DefOpc == PPC::XXPERMDIs && in simplifyCode()
757 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
769 (DefOpc == PPC::VSPLTB || DefOpc == PPC::VSPLTH || in simplifyCode()
770 DefOpc == PPC::VSPLTW || DefOpc == PPC::XXSPLTW || in simplifyCode()
771 DefOpc == PPC::VSPLTISB || DefOpc == PPC::VSPLTISH || in simplifyCode()
772 DefOpc == PPC::VSPLTISW)) { in simplifyCode()
779 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
793 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
801 case PPC::VSPLTB: in simplifyCode()
802 case PPC::VSPLTH: in simplifyCode()
803 case PPC::XXSPLTW: { in simplifyCode()
805 unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2; in simplifyCode()
815 if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS) in simplifyCode()
821 return Splt && (Splt->getOpcode() == PPC::LXVWSX || in simplifyCode()
822 Splt->getOpcode() == PPC::XXSPLTW); in simplifyCode()
825 (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) || in simplifyCode()
826 (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) || in simplifyCode()
827 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) || in simplifyCode()
828 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) || in simplifyCode()
829 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)|| in simplifyCode()
830 (MyOpcode == PPC::XXSPLTW && isConvertOfSplat()); in simplifyCode()
836 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
845 if (DefOpcode == PPC::XXSLDWI) { in simplifyCode()
851 MI.getOperand(MyOpcode == PPC::XXSPLTW ? 2 : 1).getImm(); in simplifyCode()
871 case PPC::XVCVDPSP: { in simplifyCode()
881 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { in simplifyCode()
899 if ((Opc == PPC::FRSP || Opc == PPC::XSRSP) && in simplifyCode()
933 case PPC::EXTSH: in simplifyCode()
934 case PPC::EXTSH8: in simplifyCode()
935 case PPC::EXTSH8_32_64: { in simplifyCode()
945 if (SrcOpcode == PPC::LHZ || SrcOpcode == PPC::LHZX) { in simplifyCode()
952 unsigned Opc = PPC::LHA; in simplifyCode()
953 bool SourceIsXForm = SrcOpcode == PPC::LHZX; in simplifyCode()
954 bool MIIs64Bit = MI.getOpcode() == PPC::EXTSH8 || in simplifyCode()
955 MI.getOpcode() == PPC::EXTSH8_32_64; in simplifyCode()
958 Opc = PPC::LHAX8; in simplifyCode()
960 Opc = PPC::LHAX; in simplifyCode()
962 Opc = PPC::LHA8; in simplifyCode()
984 case PPC::EXTSW: in simplifyCode()
985 case PPC::EXTSW_32: in simplifyCode()
986 case PPC::EXTSW_32_64: { in simplifyCode()
996 if (SrcOpcode == PPC::LWZ || SrcOpcode == PPC::LWZX) { in simplifyCode()
1021 unsigned Opc = PPC::LWA_32; in simplifyCode()
1022 bool SourceIsXForm = SrcOpcode == PPC::LWZX; in simplifyCode()
1023 bool MIIs64Bit = MI.getOpcode() == PPC::EXTSW || in simplifyCode()
1024 MI.getOpcode() == PPC::EXTSW_32_64; in simplifyCode()
1027 Opc = PPC::LWAX; in simplifyCode()
1029 Opc = PPC::LWAX_32; in simplifyCode()
1031 Opc = PPC::LWA; in simplifyCode()
1033 if (!IsWordAligned && (Opc == PPC::LWA || Opc == PPC::LWA_32)) in simplifyCode()
1053 } else if (MI.getOpcode() == PPC::EXTSW_32_64 && in simplifyCode()
1059 MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass); in simplifyCode()
1060 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), in simplifyCode()
1062 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG), in simplifyCode()
1066 .addImm(PPC::sub_32); in simplifyCode()
1073 case PPC::RLDICL: { in simplifyCode()
1090 if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG && in simplifyCode()
1097 if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break; in simplifyCode()
1100 if (SubRegMI->getOpcode() == PPC::COPY) { in simplifyCode()
1112 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
1127 case PPC::ADD4: in simplifyCode()
1128 case PPC::ADD8: { in simplifyCode()
1133 return DefPhiMI && (DefPhiMI->getOpcode() == PPC::PHI) && in simplifyCode()
1150 (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8) in simplifyCode()
1169 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode()
1170 ? &PPC::G8RC_and_G8RC_NOX0RegClass in simplifyCode()
1171 : &PPC::GPRC_and_GPRC_NOR0RegClass; in simplifyCode()
1184 if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8) in simplifyCode()
1187 assert((LiMI->getOpcode() == PPC::LI || in simplifyCode()
1188 LiMI->getOpcode() == PPC::LI8) && in simplifyCode()
1192 LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI in simplifyCode()
1193 : PPC::ADDI8)); in simplifyCode()
1203 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
1213 case PPC::RLDICR: { in simplifyCode()
1218 case PPC::ANDI_rec: in simplifyCode()
1219 case PPC::ANDI8_rec: in simplifyCode()
1220 case PPC::ANDIS_rec: in simplifyCode()
1221 case PPC::ANDIS8_rec: { in simplifyCode()
1232 if (SrcOpCode != PPC::RLDICL && SrcOpCode != PPC::RLDICR) in simplifyCode()
1244 if (MI.getOpcode() == PPC::ANDIS_rec || in simplifyCode()
1245 MI.getOpcode() == PPC::ANDIS8_rec) in simplifyCode()
1254 (SrcOpCode == PPC::RLDICL && (RZeroAndImm + ImmSrc > 63)) || in simplifyCode()
1255 (SrcOpCode == PPC::RLDICR && LZeroAndImm > ImmSrc); in simplifyCode()
1261 ((SrcOpCode == PPC::RLDICL && LZeroAndImm >= ImmSrc) || in simplifyCode()
1262 (SrcOpCode == PPC::RLDICR && (RZeroAndImm + ImmSrc > 63))); in simplifyCode()
1280 case PPC::RLWINM: in simplifyCode()
1281 case PPC::RLWINM_rec: in simplifyCode()
1282 case PPC::RLWINM8: in simplifyCode()
1283 case PPC::RLWINM8_rec: { in simplifyCode()
1288 : PPC::NoRegister; in simplifyCode()
1304 case PPC::TDI: in simplifyCode()
1305 case PPC::TWI: in simplifyCode()
1306 case PPC::TD: in simplifyCode()
1307 case PPC::TW: { in simplifyCode()
1314 if (!(LiMI1 && (LiMI1->getOpcode() == PPC::LI || in simplifyCode()
1315 LiMI1->getOpcode() == PPC::LI8))) in simplifyCode()
1318 !(LiMI2 && (LiMI2->getOpcode() == PPC::LI || in simplifyCode()
1319 LiMI2->getOpcode() == PPC::LI8))) in simplifyCode()
1339 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::TRAP)); in simplifyCode()
1383 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); in isEqOrNe()
1384 unsigned PredCond = PPC::getPredicateCondition(Pred); in isEqOrNe()
1385 return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE); in isEqOrNe()
1389 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || in isSupportedCmpOp()
1390 opCode == PPC::CMPLW || opCode == PPC::CMPW || in isSupportedCmpOp()
1391 opCode == PPC::CMPLDI || opCode == PPC::CMPDI || in isSupportedCmpOp()
1392 opCode == PPC::CMPLWI || opCode == PPC::CMPWI); in isSupportedCmpOp()
1396 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || in is64bitCmpOp()
1397 opCode == PPC::CMPLDI || opCode == PPC::CMPDI); in is64bitCmpOp()
1401 return (opCode == PPC::CMPD || opCode == PPC::CMPW || in isSignedCmpOp()
1402 opCode == PPC::CMPDI || opCode == PPC::CMPWI); in isSignedCmpOp()
1406 if (opCode == PPC::CMPLD) return PPC::CMPD; in getSignedCmpOpCode()
1407 if (opCode == PPC::CMPLW) return PPC::CMPW; in getSignedCmpOpCode()
1408 if (opCode == PPC::CMPLDI) return PPC::CMPDI; in getSignedCmpOpCode()
1409 if (opCode == PPC::CMPLWI) return PPC::CMPWI; in getSignedCmpOpCode()
1421 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); in getPredicateToDecImm()
1422 unsigned PredCond = PPC::getPredicateCondition(Pred); in getPredicateToDecImm()
1423 unsigned PredHint = PPC::getPredicateHint(Pred); in getPredicateToDecImm()
1424 if (PredCond == PPC::PRED_GE) in getPredicateToDecImm()
1425 return PPC::getPredicate(PPC::PRED_GT, PredHint); in getPredicateToDecImm()
1426 if (PredCond == PPC::PRED_LT) in getPredicateToDecImm()
1427 return PPC::getPredicate(PPC::PRED_LE, PredHint); in getPredicateToDecImm()
1440 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); in getPredicateToIncImm()
1441 unsigned PredCond = PPC::getPredicateCondition(Pred); in getPredicateToIncImm()
1442 unsigned PredHint = PPC::getPredicateHint(Pred); in getPredicateToIncImm()
1443 if (PredCond == PPC::PRED_GT) in getPredicateToIncImm()
1444 return PPC::getPredicate(PPC::PRED_GE, PredHint); in getPredicateToIncImm()
1445 if (PredCond == PPC::PRED_LE) in getPredicateToIncImm()
1446 return PPC::getPredicate(PPC::PRED_LT, PredHint); in getPredicateToIncImm()
1472 if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) { in getSrcVReg()
1498 (*BII).getOpcode() == PPC::BCC && in eligibleForCompareElimination()
1570 if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI) in eligibleForCompareElimination()
1726 PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm(); in eliminateRedundantCompare()
1727 NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred); in eliminateRedundantCompare()
1845 assert(Inst->getOpcode() == PPC::PHI && in eliminateRedundantCompare()
1856 Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass); in eliminateRedundantCompare()
1858 TII->get(PPC::PHI), NewVReg) in eliminateRedundantCompare()
1898 if (MI.getOpcode() != PPC::RLDICR) in emitRLDICWhenLoweringJumpTables()
1906 if (SrcMI->getOpcode() != PPC::RLDICL) in emitRLDICWhenLoweringJumpTables()
1939 MI.setDesc(TII->get(PPC::RLDIC)); in emitRLDICWhenLoweringJumpTables()
1971 if (MI.getOpcode() != PPC::RLDICR) in combineSEXTAndSHL()
1994 if (SrcMI->getOpcode() != PPC::EXTSW && in combineSEXTAndSHL()
1995 SrcMI->getOpcode() != PPC::EXTSW_32_64) in combineSEXTAndSHL()
2015 SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI) in combineSEXTAndSHL()
2016 : TII->get(PPC::EXTSWSLI_32_64), in combineSEXTAndSHL()