Lines Matching +full:0 +full:xb
5 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
28 // * [FR|R|V|X|B][A-Z] - register source (i.e. FRA, RA, XB, etc.)
49 // and sources (XA, XB) that are all 6-bits. The destination and
62 def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>,
66 SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>,
70 SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>
73 SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2>
76 SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2>
79 SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1>
103 SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
114 field bits<64> SoftFail = 0;
115 bit PCRel = 0; // Default value, set by isPCRel.
123 let Inst{0-5} = pref;
126 bits<1> PPC970_First = 0;
127 bits<1> PPC970_Single = 0;
128 bits<1> PPC970_Cracked = 0;
129 bits<3> PPC970_Unit = 0;
133 let TSFlags{0} = PPC970_First;
145 bit Interpretation64Bit = 0;
157 bit RC = 0;
195 let Inst{8-10} = 0;
197 let Inst{12-13} = 0;
201 let Inst{38-42} = RST{4-0};
203 let Inst{48-63} = D{15-0}; // d1
217 let Inst{8-10} = 0;
219 let Inst{12-13} = 0;
225 let Inst{48-63} = SI{15-0};
238 let Inst{8-10} = 0;
239 let Inst{11} = 0;
240 let Inst{12-13} = 0;
245 let Inst{43-47} = 0;
246 let Inst{48-63} = SI{15-0};
253 !strconcat(asmstr, ", 0"), itin, []>;
268 let Inst{6-10} = 0;
270 let Inst{12-13} = 0;
274 let Inst{38-42} = RST{4-0};
276 let Inst{48-63} = D{15-0}; // d1
279 // 8LS:D-Form: [ 1 0 0 // R // d0
292 let Inst{6-7} = 0;
293 let Inst{8} = 0;
294 let Inst{9-10} = 0; // reserved
296 let Inst{12-13} = 0; // reserved
301 let Inst{38-42} = XST{4-0};
303 let Inst{48-63} = D{15-0}; // d1
315 let Inst{6-10} = XT{4-0};
328 bits<6> XB;
336 let Inst{8} = 0;
337 let Inst{9-11} = 0;
338 let Inst{12-13} = 0;
339 let Inst{14-23} = 0;
343 let Inst{38-42} = XT{4-0};
344 let Inst{43-47} = XA{4-0};
345 let Inst{48-52} = XB{4-0};
346 let Inst{53-57} = XC{4-0};
350 let Inst{62} = XB{5};
364 let Inst{11-12} = 0;
396 let Inst{9-10} = 0;
438 // 8RR:D-Form: [ 1 1 0 // // imm0
451 let Inst{8-11} = 0;
452 let Inst{12-13} = 0; // reserved
453 let Inst{14-15} = 0; // reserved
457 let Inst{38-42} = XT{4-0};
460 let Inst{48-63} = IMM32{15-0};
463 // 8RR:D-Form: [ 1 1 0 // // imm0
477 let Inst{8-11} = 0;
478 let Inst{12-13} = 0; // reserved
479 let Inst{14-15} = 0; // reserved
483 let Inst{38-42} = XT{4-0};
487 let Inst{48-63} = IMM32{15-0};
495 bits<6> XB;
502 let Inst{8-11} = 0;
503 let Inst{12-13} = 0;
504 let Inst{14-31} = 0;
507 let Inst{38-42} = XT{4-0};
508 let Inst{43-47} = XA{4-0};
509 let Inst{48-52} = XB{4-0};
510 let Inst{53-57} = XC{4-0};
514 let Inst{62} = XB{5};
524 bits<6> XB;
532 let Inst{8-11} = 0;
533 let Inst{12-13} = 0;
534 let Inst{14-28} = 0;
538 let Inst{38-42} = XT{4-0};
539 let Inst{43-47} = XA{4-0};
540 let Inst{48-52} = XB{4-0};
541 let Inst{53-57} = XC{4-0};
545 let Inst{62} = XB{5};
555 bits<6> XB;
560 let Inst{9-10} = 0;
562 let Inst{16-20} = XB{4-0};
564 let Inst{30} = XB{5};
565 let Inst{31} = 0;
574 let RB = 0;
582 !strconcat(asmstr, ", 0"), itin, []>;
588 let RA = 0 in
599 !strconcat(asmstr, ", 0"), itin, []>;
605 let RA = 0 in
616 !strconcat(asmstr, ", 0"), itin, []>;
622 let RA = 0 in
633 dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);
658 let mayLoad = 1, mayStore = 0 in {
720 let mayStore = 1, mayLoad = 0 in {
762 let mayLoad = 1, mayStore = 0 in {
774 let mayStore = 1, mayLoad = 0 in {
789 let mayLoad = 1, mayStore = 0 in {
808 let mayStore = 1, mayLoad = 0 in {
826 8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
828 "xxpermx $XT, $XA, $XB, $XC, $IMM",
831 8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
832 vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",
835 8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
836 vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",
839 8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
840 vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",
843 8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
844 vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC",
857 let Inst{6-9} = XTp{3-0};
872 let Inst{6-9} = XTp{3-0};
877 let Inst{31} = 0;
890 let Inst{6-10} = 0;
892 let Inst{12-13} = 0;
896 let Inst{38-41} = XTp{3-0};
899 let Inst{48-63} = D{15-0};
907 !strconcat(asmstr, ", 0"), itin, []>;
913 let RA = 0 in
930 let Inst{9-10} = 0;
932 let Inst{16-20} = 0;
934 let Inst{31} = 0;
946 let Inst{6-10} = XT{4-0};
959 bits<6> XB;
964 let Inst{9-10} = 0;
965 let Inst{11-15} = XA{4-0};
966 let Inst{16-20} = XB{4-0};
969 let Inst{30} = XB{5};
970 let Inst{31} = 0;
979 bits<6> XB;
989 let Inst{12-15} = 0;
991 let Inst{18-23} = 0;
997 let Inst{41-42} = 0;
998 let Inst{43-47} = XA{4-0};
999 let Inst{48-52} = XB{4-0};
1002 let Inst{62} = XB{5};
1003 let Inst{63} = 0;
1012 bits<6> XB;
1021 let Inst{12-23} = 0;
1027 let Inst{41-42} = 0;
1028 let Inst{43-47} = XA{4-0};
1029 let Inst{48-52} = XB{4-0};
1032 let Inst{62} = XB{5};
1033 let Inst{63} = 0;
1042 bits<6> XB;
1051 let Inst{12-23} = 0;
1054 let Inst{30-31} = 0;
1058 let Inst{41-42} = 0;
1059 let Inst{43-47} = XA{4-0};
1060 let Inst{48-52} = XB{4-0};
1063 let Inst{62} = XB{5};
1064 let Inst{63} = 0;
1073 bits<6> XB;
1083 let Inst{12-15} = 0;
1090 let Inst{41-42} = 0;
1091 let Inst{43-47} = XA{4-0};
1092 let Inst{48-52} = XB{4-0};
1095 let Inst{62} = XB{5};
1096 let Inst{63} = 0;
1105 bits<6> XB;
1115 let Inst{12-15} = 0;
1117 let Inst{20-23} = 0;
1123 let Inst{41-42} = 0;
1124 let Inst{43-47} = XA{4-0};
1125 let Inst{48-52} = XB{4-0};
1128 let Inst{62} = XB{5};
1129 let Inst{63} = 0;
1150 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)),
1155 let mayLoad = 1, mayStore = 0 in {
1156 def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp),
1164 let mayLoad = 0, mayStore = 1 in {
1173 let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {
1182 let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in {
1217 (PLBZpc $ga, 0)>;
1219 (PLBZpc $ga, 0)>;
1221 (PLBZpc $ga, 0)>;
1223 (PLBZpc $ga, 0)>;
1225 (PLHApc $ga, 0)>;
1227 (PLHZpc $ga, 0)>;
1229 (PLHZpc $ga, 0)>;
1230 def : Pat<(i32 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLWZpc $ga, 0)>;
1234 (PSTBpc $RS, $ga, 0)>;
1236 (PSTHpc $RS, $ga, 0)>;
1238 (PSTWpc $RS, $ga, 0)>;
1242 (PLBZ8pc $ga, 0)>;
1244 (PLBZ8pc $ga, 0)>;
1246 (PLBZ8pc $ga, 0)>;
1248 (PLBZ8pc $ga, 0)>;
1250 (PLHA8pc $ga, 0)>;
1252 (PLHZ8pc $ga, 0)>;
1254 (PLHZ8pc $ga, 0)>;
1256 (PLWZ8pc $ga, 0)>;
1258 (PLWA8pc $ga, 0)>;
1260 (PLWZ8pc $ga, 0)>;
1261 def : Pat<(i64 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLDpc $ga, 0)>;
1265 (PSTB8pc $RS, $ga, 0)>;
1267 (PSTH8pc $RS, $ga, 0)>;
1269 (PSTW8pc $RS, $ga, 0)>;
1271 (PSTDpc $RS, $ga, 0)>;
1275 (PLBZpc $ga, 0)>;
1277 (PLHZpc $ga, 0)>;
1279 (PLWZpc $ga, 0)>;
1281 (PLDpc $ga, 0)>;
1285 (PSTBpc $RS, $ga, 0)>;
1287 (PSTHpc $RS, $ga, 0)>;
1289 (PSTWpc $RS, $ga, 0)>;
1291 (PSTB8pc $RS, $ga, 0)>;
1293 (PSTH8pc $RS, $ga, 0)>;
1295 (PSTW8pc $RS, $ga, 0)>;
1297 (PSTDpc $RS, $ga, 0)>;
1301 def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;
1304 def : Pat<(PPCtlsdynamatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;
1313 def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>;
1317 (PSTFSpc $FRS, $ga, 0)>;
1321 (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>;
1322 def : Pat<(f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFDpc $addr, 0)>;
1326 (PSTFDpc $FRS, $ga, 0)>;
1329 (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>;
1335 (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>;
1339 (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>;
1342 def : Pat<(v4i32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1346 (PSTXVpc $XS, $ga, 0)>;
1349 def : Pat<(v2i64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1353 (PSTXVpc $XS, $ga, 0)>;
1356 def : Pat<(v4f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1360 (PSTXVpc $XS, $ga, 0)>;
1363 def : Pat<(v2f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1367 (PSTXVpc $XS, $ga, 0)>;
1371 (PSTXSDpc $src, $dst, 0)>;
1373 (PSTXSDpc (COPY_TO_REGCLASS $src, VFRC), $dst, 0)>;
1389 8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),
1427 def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
1447 defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$VT), (ins vrrc:$VB),
1567 def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$VD), (ins vrrc:$VB),
1721 8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1723 "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral,
1725 v2i64:$XB, v2i64:$XC, timm:$IMM))]>;
1817 def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
1818 "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
1836 let mayLoad = 1, mayStore = 0 in {
1843 let mayLoad = 0, mayStore = 1 in {
1918 def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
2068 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)),
2069 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
2070 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
2071 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
2073 (RLDICL_32 (BRH $RS), 0, 48)>;
2075 (RLDICL_32_64 (BRH $RS), 0, 48)>;
2100 // Store element 0 of a VSX register to memory
2101 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), ForceXForm:$dst),
2103 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), ForceXForm:$dst),
2105 def : Pat<(store (i32 (extractelt v4i32:$src, 0)), ForceXForm:$dst),
2107 def : Pat<(store (f32 (extractelt v4f32:$src, 0)), ForceXForm:$dst),
2109 def : Pat<(store (i64 (extractelt v2i64:$src, 0)), ForceXForm:$dst),
2111 def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst),
2113 // Load element 0 of a VSX register to memory
2123 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src),
2175 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX(IMPLICIT_DEF), 0,
2181 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX (IMPLICIT_DEF), 0,
2387 dag Sub32Left1 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 1, 0, 30);
2388 dag Sub32Left2 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 2, 0, 29);
2389 dag Left1 = (RLWINM $rB, 1, 0, 30);
2390 dag Left2 = (RLWINM $rB, 2, 0, 29);
2391 dag Left3 = (RLWINM8 $rB, 3, 0, 28);
2418 foreach Idx = [0, 1, 2, 3] in {
2422 foreach i = [0, 1] in
2468 foreach Idx = [0, 1, 2, 3] in {
2474 foreach Idx = [0, 1] in
2485 def : InstAlias<"wait", (WAITP10 0, 0)>;
2486 def : InstAlias<"wait 0", (WAITP10 0, 0), 0>;
2487 def : InstAlias<"wait 1", (WAITP10 1, 0), 0>;
2488 def : InstAlias<"waitrsv", (WAITP10 1, 0)>;
2489 def : InstAlias<"pause_short", (WAITP10 2, 0), 0>;
2491 def : InstAlias<"sync", (SYNCP10 0, 0)>;
2492 def : InstAlias<"hwsync", (SYNCP10 0, 0), 0>;
2493 def : InstAlias<"wsync", (SYNCP10 1, 0), 0>;
2494 def : InstAlias<"ptesync", (SYNCP10 2, 0)>;
2495 def : InstAlias<"phwsync", (SYNCP10 4, 0)>;
2496 def : InstAlias<"plwsync", (SYNCP10 5, 0)>;
2497 def : InstAlias<"sync $L", (SYNCP10 u3imm:$L, 0)>;
2499 def : InstAlias<"stcisync", (SYNCP10 0, 2)>;
2500 def : InstAlias<"stsync", (SYNCP10 0, 3)>;